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author | Linus Torvalds <torvalds@linux-foundation.org> | 2018-04-02 20:20:12 -0700 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2018-04-02 20:20:12 -0700 |
commit | f5a8eb632b562bd9c16c389f5db3a5260fba4157 (patch) | |
tree | 82687234d772ff8f72a31e598fe16553885c56c9 /arch/metag/include/asm/spinlock_lnkget.h | |
parent | Merge tag 'nds32-for-linus-4.17' of git://git.kernel.org/pub/scm/linux/kernel/git/greentime/linux (diff) | |
parent | MAINTAINERS: UNICORE32: Change email account (diff) | |
download | wireguard-linux-f5a8eb632b562bd9c16c389f5db3a5260fba4157.tar.xz wireguard-linux-f5a8eb632b562bd9c16c389f5db3a5260fba4157.zip |
Merge tag 'arch-removal' of git://git.kernel.org/pub/scm/linux/kernel/git/arnd/asm-generic
Pul removal of obsolete architecture ports from Arnd Bergmann:
"This removes the entire architecture code for blackfin, cris, frv,
m32r, metag, mn10300, score, and tile, including the associated device
drivers.
I have been working with the (former) maintainers for each one to
ensure that my interpretation was right and the code is definitely
unused in mainline kernels. Many had fond memories of working on the
respective ports to start with and getting them included in upstream,
but also saw no point in keeping the port alive without any users.
In the end, it seems that while the eight architectures are extremely
different, they all suffered the same fate: There was one company in
charge of an SoC line, a CPU microarchitecture and a software
ecosystem, which was more costly than licensing newer off-the-shelf
CPU cores from a third party (typically ARM, MIPS, or RISC-V). It
seems that all the SoC product lines are still around, but have not
used the custom CPU architectures for several years at this point. In
contrast, CPU instruction sets that remain popular and have actively
maintained kernel ports tend to all be used across multiple licensees.
[ See the new nds32 port merged in the previous commit for the next
generation of "one company in charge of an SoC line, a CPU
microarchitecture and a software ecosystem" - Linus ]
The removal came out of a discussion that is now documented at
https://lwn.net/Articles/748074/. Unlike the original plans, I'm not
marking any ports as deprecated but remove them all at once after I
made sure that they are all unused. Some architectures (notably tile,
mn10300, and blackfin) are still being shipped in products with old
kernels, but those products will never be updated to newer kernel
releases.
After this series, we still have a few architectures without mainline
gcc support:
- unicore32 and hexagon both have very outdated gcc releases, but the
maintainers promised to work on providing something newer. At least
in case of hexagon, this will only be llvm, not gcc.
- openrisc, risc-v and nds32 are still in the process of finishing
their support or getting it added to mainline gcc in the first
place. They all have patched gcc-7.3 ports that work to some
degree, but complete upstream support won't happen before gcc-8.1.
Csky posted their first kernel patch set last week, their situation
will be similar
[ Palmer Dabbelt points out that RISC-V support is in mainline gcc
since gcc-7, although gcc-7.3.0 is the recommended minimum - Linus ]"
This really says it all:
2498 files changed, 95 insertions(+), 467668 deletions(-)
* tag 'arch-removal' of git://git.kernel.org/pub/scm/linux/kernel/git/arnd/asm-generic: (74 commits)
MAINTAINERS: UNICORE32: Change email account
staging: iio: remove iio-trig-bfin-timer driver
tty: hvc: remove tile driver
tty: remove bfin_jtag_comm and hvc_bfin_jtag drivers
serial: remove tile uart driver
serial: remove m32r_sio driver
serial: remove blackfin drivers
serial: remove cris/etrax uart drivers
usb: Remove Blackfin references in USB support
usb: isp1362: remove blackfin arch glue
usb: musb: remove blackfin port
usb: host: remove tilegx platform glue
pwm: remove pwm-bfin driver
i2c: remove bfin-twi driver
spi: remove blackfin related host drivers
watchdog: remove bfin_wdt driver
can: remove bfin_can driver
mmc: remove bfin_sdh driver
input: misc: remove blackfin rotary driver
input: keyboard: remove bf54x driver
...
Diffstat (limited to 'arch/metag/include/asm/spinlock_lnkget.h')
-rw-r--r-- | arch/metag/include/asm/spinlock_lnkget.h | 213 |
1 files changed, 0 insertions, 213 deletions
diff --git a/arch/metag/include/asm/spinlock_lnkget.h b/arch/metag/include/asm/spinlock_lnkget.h deleted file mode 100644 index dfd780eab350..000000000000 --- a/arch/metag/include/asm/spinlock_lnkget.h +++ /dev/null @@ -1,213 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __ASM_SPINLOCK_LNKGET_H -#define __ASM_SPINLOCK_LNKGET_H - -/* - * None of these asm statements clobber memory as LNKSET writes around - * the cache so the memory it modifies cannot safely be read by any means - * other than these accessors. - */ - -static inline int arch_spin_is_locked(arch_spinlock_t *lock) -{ - int ret; - - asm volatile ("LNKGETD %0, [%1]\n" - "TST %0, #1\n" - "MOV %0, #1\n" - "XORZ %0, %0, %0\n" - : "=&d" (ret) - : "da" (&lock->lock) - : "cc"); - return ret; -} - -static inline void arch_spin_lock(arch_spinlock_t *lock) -{ - int tmp; - - asm volatile ("1: LNKGETD %0,[%1]\n" - " TST %0, #1\n" - " ADD %0, %0, #1\n" - " LNKSETDZ [%1], %0\n" - " BNZ 1b\n" - " DEFR %0, TXSTAT\n" - " ANDT %0, %0, #HI(0x3f000000)\n" - " CMPT %0, #HI(0x02000000)\n" - " BNZ 1b\n" - : "=&d" (tmp) - : "da" (&lock->lock) - : "cc"); - - smp_mb(); -} - -/* Returns 0 if failed to acquire lock */ -static inline int arch_spin_trylock(arch_spinlock_t *lock) -{ - int tmp; - - asm volatile (" LNKGETD %0,[%1]\n" - " TST %0, #1\n" - " ADD %0, %0, #1\n" - " LNKSETDZ [%1], %0\n" - " BNZ 1f\n" - " DEFR %0, TXSTAT\n" - " ANDT %0, %0, #HI(0x3f000000)\n" - " CMPT %0, #HI(0x02000000)\n" - " MOV %0, #1\n" - "1: XORNZ %0, %0, %0\n" - : "=&d" (tmp) - : "da" (&lock->lock) - : "cc"); - - smp_mb(); - - return tmp; -} - -static inline void arch_spin_unlock(arch_spinlock_t *lock) -{ - smp_mb(); - - asm volatile (" SETD [%0], %1\n" - : - : "da" (&lock->lock), "da" (0) - : "memory"); -} - -/* - * RWLOCKS - * - * - * Write locks are easy - we just set bit 31. When unlocking, we can - * just write zero since the lock is exclusively held. - */ - -static inline void arch_write_lock(arch_rwlock_t *rw) -{ - int tmp; - - asm volatile ("1: LNKGETD %0,[%1]\n" - " CMP %0, #0\n" - " ADD %0, %0, %2\n" - " LNKSETDZ [%1], %0\n" - " BNZ 1b\n" - " DEFR %0, TXSTAT\n" - " ANDT %0, %0, #HI(0x3f000000)\n" - " CMPT %0, #HI(0x02000000)\n" - " BNZ 1b\n" - : "=&d" (tmp) - : "da" (&rw->lock), "bd" (0x80000000) - : "cc"); - - smp_mb(); -} - -static inline int arch_write_trylock(arch_rwlock_t *rw) -{ - int tmp; - - asm volatile (" LNKGETD %0,[%1]\n" - " CMP %0, #0\n" - " ADD %0, %0, %2\n" - " LNKSETDZ [%1], %0\n" - " BNZ 1f\n" - " DEFR %0, TXSTAT\n" - " ANDT %0, %0, #HI(0x3f000000)\n" - " CMPT %0, #HI(0x02000000)\n" - " MOV %0,#1\n" - "1: XORNZ %0, %0, %0\n" - : "=&d" (tmp) - : "da" (&rw->lock), "bd" (0x80000000) - : "cc"); - - smp_mb(); - - return tmp; -} - -static inline void arch_write_unlock(arch_rwlock_t *rw) -{ - smp_mb(); - - asm volatile (" SETD [%0], %1\n" - : - : "da" (&rw->lock), "da" (0) - : "memory"); -} - -/* - * Read locks are a bit more hairy: - * - Exclusively load the lock value. - * - Increment it. - * - Store new lock value if positive, and we still own this location. - * If the value is negative, we've already failed. - * - If we failed to store the value, we want a negative result. - * - If we failed, try again. - * Unlocking is similarly hairy. We may have multiple read locks - * currently active. However, we know we won't have any write - * locks. - */ -static inline void arch_read_lock(arch_rwlock_t *rw) -{ - int tmp; - - asm volatile ("1: LNKGETD %0,[%1]\n" - " ADDS %0, %0, #1\n" - " LNKSETDPL [%1], %0\n" - " BMI 1b\n" - " DEFR %0, TXSTAT\n" - " ANDT %0, %0, #HI(0x3f000000)\n" - " CMPT %0, #HI(0x02000000)\n" - " BNZ 1b\n" - : "=&d" (tmp) - : "da" (&rw->lock) - : "cc"); - - smp_mb(); -} - -static inline void arch_read_unlock(arch_rwlock_t *rw) -{ - int tmp; - - smp_mb(); - - asm volatile ("1: LNKGETD %0,[%1]\n" - " SUB %0, %0, #1\n" - " LNKSETD [%1], %0\n" - " DEFR %0, TXSTAT\n" - " ANDT %0, %0, #HI(0x3f000000)\n" - " CMPT %0, #HI(0x02000000)\n" - " BNZ 1b\n" - : "=&d" (tmp) - : "da" (&rw->lock) - : "cc", "memory"); -} - -static inline int arch_read_trylock(arch_rwlock_t *rw) -{ - int tmp; - - asm volatile (" LNKGETD %0,[%1]\n" - " ADDS %0, %0, #1\n" - " LNKSETDPL [%1], %0\n" - " BMI 1f\n" - " DEFR %0, TXSTAT\n" - " ANDT %0, %0, #HI(0x3f000000)\n" - " CMPT %0, #HI(0x02000000)\n" - " MOV %0,#1\n" - " BZ 2f\n" - "1: MOV %0,#0\n" - "2:\n" - : "=&d" (tmp) - : "da" (&rw->lock) - : "cc"); - - smp_mb(); - - return tmp; -} - -#endif /* __ASM_SPINLOCK_LNKGET_H */ |