Merge tag 'arch-removal' of git://git.kernel.org/pub/scm/linux/kernel/git/arnd/asm-generic

Pul removal of obsolete architecture ports from Arnd Bergmann:
 "This removes the entire architecture code for blackfin, cris, frv,
  m32r, metag, mn10300, score, and tile, including the associated device
  drivers.

  I have been working with the (former) maintainers for each one to
  ensure that my interpretation was right and the code is definitely
  unused in mainline kernels. Many had fond memories of working on the
  respective ports to start with and getting them included in upstream,
  but also saw no point in keeping the port alive without any users.

  In the end, it seems that while the eight architectures are extremely
  different, they all suffered the same fate: There was one company in
  charge of an SoC line, a CPU microarchitecture and a software
  ecosystem, which was more costly than licensing newer off-the-shelf
  CPU cores from a third party (typically ARM, MIPS, or RISC-V). It
  seems that all the SoC product lines are still around, but have not
  used the custom CPU architectures for several years at this point. In
  contrast, CPU instruction sets that remain popular and have actively
  maintained kernel ports tend to all be used across multiple licensees.

  [ See the new nds32 port merged in the previous commit for the next
    generation of "one company in charge of an SoC line, a CPU
    microarchitecture and a software ecosystem"   - Linus ]

  The removal came out of a discussion that is now documented at
  https://lwn.net/Articles/748074/. Unlike the original plans, I'm not
  marking any ports as deprecated but remove them all at once after I
  made sure that they are all unused. Some architectures (notably tile,
  mn10300, and blackfin) are still being shipped in products with old
  kernels, but those products will never be updated to newer kernel
  releases.

  After this series, we still have a few architectures without mainline
  gcc support:

   - unicore32 and hexagon both have very outdated gcc releases, but the
     maintainers promised to work on providing something newer. At least
     in case of hexagon, this will only be llvm, not gcc.

   - openrisc, risc-v and nds32 are still in the process of finishing
     their support or getting it added to mainline gcc in the first
     place. They all have patched gcc-7.3 ports that work to some
     degree, but complete upstream support won't happen before gcc-8.1.
     Csky posted their first kernel patch set last week, their situation
     will be similar

  [ Palmer Dabbelt points out that RISC-V support is in mainline gcc
    since gcc-7, although gcc-7.3.0 is the recommended minimum  - Linus ]"

This really says it all:

 2498 files changed, 95 insertions(+), 467668 deletions(-)

* tag 'arch-removal' of git://git.kernel.org/pub/scm/linux/kernel/git/arnd/asm-generic: (74 commits)
  MAINTAINERS: UNICORE32: Change email account
  staging: iio: remove iio-trig-bfin-timer driver
  tty: hvc: remove tile driver
  tty: remove bfin_jtag_comm and hvc_bfin_jtag drivers
  serial: remove tile uart driver
  serial: remove m32r_sio driver
  serial: remove blackfin drivers
  serial: remove cris/etrax uart drivers
  usb: Remove Blackfin references in USB support
  usb: isp1362: remove blackfin arch glue
  usb: musb: remove blackfin port
  usb: host: remove tilegx platform glue
  pwm: remove pwm-bfin driver
  i2c: remove bfin-twi driver
  spi: remove blackfin related host drivers
  watchdog: remove bfin_wdt driver
  can: remove bfin_can driver
  mmc: remove bfin_sdh driver
  input: misc: remove blackfin rotary driver
  input: keyboard: remove bf54x driver
  ...

1 files changed, 0 insertions, 106 deletions

diff --git a/arch/metag/kernel/perf/perf_event.h b/arch/metag/kernel/perf/perf_event.h
deleted file mode 100644
index fd10a1345b67..000000000000
--- a/arch/metag/kernel/perf/perf_event.h
+++ /dev/null
@@ -1,106 +0,0 @@
-/*
- * Meta performance counter support.
- *  Copyright (C) 2012 Imagination Technologies Ltd
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-
-#ifndef METAG_PERF_EVENT_H_
-#define METAG_PERF_EVENT_H_
-
-#include <linux/kernel.h>
-#include <linux/interrupt.h>
-#include <linux/perf_event.h>
-
-/* For performance counter definitions */
-#include <asm/metag_mem.h>
-
-/*
- * The Meta core has two performance counters, with 24-bit resolution. Newer
- * cores generate an overflow interrupt on transition from 0xffffff to 0.
- *
- * Each counter consists of the counter id, hardware thread id, and the count
- * itself; each counter can be assigned to multiple hardware threads at any
- * one time, with the returned count being an aggregate of events. A small
- * number of events are thread global, i.e. they count the aggregate of all
- * threads' events, regardless of the thread selected.
- *
- * Newer cores can store an arbitrary 24-bit number in the counter, whereas
- * older cores will clear the counter bits on write.
- *
- * We also have a pseudo-counter in the form of the thread active cycles
- * counter (which, incidentally, is also bound to
- */
-
-#define MAX_HWEVENTS		3
-#define MAX_PERIOD		((1UL << 24) - 1)
-#define METAG_INST_COUNTER	(MAX_HWEVENTS - 1)
-
-/**
- * struct cpu_hw_events - a processor core's performance events
- * @events:	an array of perf_events active for a given index.
- * @used_mask:	a bitmap of in-use counters.
- * @pmu_lock:	a perf counter lock
- *
- * This is a per-cpu/core structure that maintains a record of its
- * performance counters' state.
- */
-struct cpu_hw_events {
-	struct perf_event	*events[MAX_HWEVENTS];
-	unsigned long		used_mask[BITS_TO_LONGS(MAX_HWEVENTS)];
-	raw_spinlock_t		pmu_lock;
-};
-
-/**
- * struct metag_pmu - the Meta PMU structure
- * @pmu:		core pmu structure
- * @name:		pmu name
- * @version:		core version
- * @handle_irq:		overflow interrupt handler
- * @enable:		enable a counter
- * @disable:		disable a counter
- * @read:		read the value of a counter
- * @write:		write a value to a counter
- * @event_map:		kernel event to counter event id map
- * @cache_events:	kernel cache counter to core cache counter map
- * @max_period:		maximum value of the counter before overflow
- * @max_events:		maximum number of counters available at any one time
- * @active_events:	number of active counters
- * @reserve_mutex:	counter reservation mutex
- *
- * This describes the main functionality and data used by the performance
- * event core.
- */
-struct metag_pmu {
-	struct pmu	pmu;
-	const char	*name;
-	u32		version;
-	irqreturn_t	(*handle_irq)(int irq_num, void *dev);
-	void		(*enable)(struct hw_perf_event *evt, int idx);
-	void		(*disable)(struct hw_perf_event *evt, int idx);
-	u64		(*read)(int idx);
-	void		(*write)(int idx, u32 val);
-	int		(*event_map)(int idx);
-	const int	(*cache_events)[PERF_COUNT_HW_CACHE_MAX]
-				[PERF_COUNT_HW_CACHE_OP_MAX]
-				[PERF_COUNT_HW_CACHE_RESULT_MAX];
-	u32		max_period;
-	int		max_events;
-	atomic_t	active_events;
-	struct mutex	reserve_mutex;
-};
-
-/* Convenience macros for accessing the perf counters */
-/* Define some convenience accessors */
-#define PERF_COUNT(x)	(PERF_COUNT0 + (sizeof(u64) * (x)))
-#define PERF_ICORE(x)	(PERF_ICORE0 + (sizeof(u64) * (x)))
-#define PERF_CHAN(x)	(PERF_CHAN0 + (sizeof(u64) * (x)))
-
-/* Cache index macros */
-#define C(x) PERF_COUNT_HW_CACHE_##x
-#define CACHE_OP_UNSUPPORTED	0xfffe
-#define CACHE_OP_NONSENSE	0xffff
-
-#endif