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| author |   Michal Simek <michal.simek@xilinx.com> | 2020-11-26 14:32:25 +0100 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2020-11-26 16:39:35 +0100 |
| commit | 05cdf457477d6603b207d91873f0a3d4c7f8c1cd (patch) | |
| tree | 187900c636e5c8b9da2fe4344cbc8658ab92541a /arch/microblaze/mm/consistent.c | |
| parent | microblaze: add support for TIF_NOTIFY_SIGNAL (diff) | |
| download | wireguard-linux-05cdf457477d6603b207d91873f0a3d4c7f8c1cd.tar.xz wireguard-linux-05cdf457477d6603b207d91873f0a3d4c7f8c1cd.zip | |
microblaze: Remove noMMU code
This configuration is obsolete and likely none is really using it. That's
why remove it to simplify code.
Note about CONFIG_MMU in hw_exception_handler.S is left intentionally
for better comment understanding.
Cc: Mike Rapoport <rppt@kernel.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Mike Rapoport <rppt@linux.ibm.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/r/43486cab370e0c0a79860120b71e0caac75a7e44.1606397528.git.michal.simek@xilinx.com
Diffstat (limited to 'arch/microblaze/mm/consistent.c')
| -rw-r--r-- | arch/microblaze/mm/consistent.c | 29 |
1 files changed, 0 insertions, 29 deletions
diff --git a/arch/microblaze/mm/consistent.c b/arch/microblaze/mm/consistent.c index 81dffe43b18c..b7ad4a98636d 100644 --- a/arch/microblaze/mm/consistent.c +++ b/arch/microblaze/mm/consistent.c @@ -21,32 +21,3 @@ void arch_dma_prep_coherent(struct page *page, size_t size) flush_dcache_range(paddr, paddr + size); } - -#ifndef CONFIG_MMU -/* - * Consistent memory allocators. Used for DMA devices that want to share - * uncached memory with the processor core. My crufty no-MMU approach is - * simple. In the HW platform we can optionally mirror the DDR up above the - * processor cacheable region. So, memory accessed in this mirror region will - * not be cached. It's alloced from the same pool as normal memory, but the - * handle we return is shifted up into the uncached region. This will no doubt - * cause big problems if memory allocated here is not also freed properly. -- JW - * - * I have to use dcache values because I can't relate on ram size: - */ -#ifdef CONFIG_XILINX_UNCACHED_SHADOW -#define UNCACHED_SHADOW_MASK (cpuinfo.dcache_high - cpuinfo.dcache_base + 1) -#else -#define UNCACHED_SHADOW_MASK 0 -#endif /* CONFIG_XILINX_UNCACHED_SHADOW */ - -void *arch_dma_set_uncached(void *ptr, size_t size) -{ - unsigned long addr = (unsigned long)ptr; - - addr |= UNCACHED_SHADOW_MASK; - if (addr > cpuinfo.dcache_base && addr < cpuinfo.dcache_high) - pr_warn("ERROR: Your cache coherent area is CACHED!!!\n"); - return (void *)addr; -} -#endif /* CONFIG_MMU */ |