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| author |   Boris Brezillon <boris.brezillon@free-electrons.com> | 2015-07-09 22:39:38 +0200 |
|---|---|---|
| committer |   Stephen Boyd <sboyd@codeaurora.org> | 2015-07-27 18:13:32 -0700 |
| commit | 57d866e606ddf2a0cd51f7140cfd8df1fdaa48f6 (patch) | |
| tree | d416f5f0399391f963b2aa4ffc03d281c3d237ad /arch/mips/alchemy/common | |
| parent | clk: change clk_ops' ->determine_rate() prototype (diff) | |
| download | wireguard-linux-57d866e606ddf2a0cd51f7140cfd8df1fdaa48f6.tar.xz wireguard-linux-57d866e606ddf2a0cd51f7140cfd8df1fdaa48f6.zip | |
clk: fix some determine_rate implementations
Some determine_rate implementations are not returning an error
when they failed to adapt the rate according to the rate request.
Fix them so that they return an error instead of silently
returning 0.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
CC: Jonathan Corbet <corbet@lwn.net>
CC: Tony Lindgren <tony@atomide.com>
CC: Ralf Baechle <ralf@linux-mips.org>
CC: "Emilio López" <emilio@elopez.com.ar>
CC: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Tero Kristo <t-kristo@ti.com>
CC: Peter De Schrijver <pdeschrijver@nvidia.com>
CC: Prashant Gaikwad <pgaikwad@nvidia.com>
CC: Stephen Warren <swarren@wwwdotorg.org>
CC: Thierry Reding <thierry.reding@gmail.com>
CC: Alexandre Courbot <gnurou@gmail.com>
CC: linux-doc@vger.kernel.org
CC: linux-kernel@vger.kernel.org
CC: linux-arm-kernel@lists.infradead.org
CC: linux-omap@vger.kernel.org
CC: linux-mips@linux-mips.org
CC: linux-tegra@vger.kernel.org
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'arch/mips/alchemy/common')
| -rw-r--r-- | arch/mips/alchemy/common/clock.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/mips/alchemy/common/clock.c b/arch/mips/alchemy/common/clock.c index 0b4cf3e9f005..7cc3eed83a1e 100644 --- a/arch/mips/alchemy/common/clock.c +++ b/arch/mips/alchemy/common/clock.c @@ -469,9 +469,13 @@ static int alchemy_clk_fgcs_detr(struct clk_hw *hw, } } + if (br < 0) + return br; + req->best_parent_rate = bpr; req->best_parent_hw = __clk_get_hw(bpc); req->rate = br; + return 0; } |