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| author |   Gregory CLEMENT <gregory.clement@bootlin.com> | 2020-11-10 12:45:02 +0100 |
|---|---|---|
| committer |   Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2020-11-12 23:31:47 +0100 |
| commit | 700364dadceb8d60ca1bb6ccd3da619a36ecdcde (patch) | |
| tree | 5fd107b7d7b9bf6b860407d02c0bdd7e11770186 /arch/mips/boot/dts/mscc/Makefile | |
| parent | dt-bindings: mips: Add Serval and Jaguar2 (diff) | |
| download | wireguard-linux-700364dadceb8d60ca1bb6ccd3da619a36ecdcde.tar.xz wireguard-linux-700364dadceb8d60ca1bb6ccd3da619a36ecdcde.zip | |
MIPS: mscc: Prepare configuration to handle more SoCs
Ocelot belongs to a family of SoC named the VCore III. In order to add
these new Soc, use the new symbol SOC_VCOREIII instead of a one
dedicated to Ocelot.
In order to avoid regression on driver building, the MSCC_OCELOT
configuration symbol is kept until the driver will be converted.
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to 'arch/mips/boot/dts/mscc/Makefile')
| -rw-r--r-- | arch/mips/boot/dts/mscc/Makefile | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/boot/dts/mscc/Makefile b/arch/mips/boot/dts/mscc/Makefile index eb71515871f6..5015ccbbfb23 100644 --- a/arch/mips/boot/dts/mscc/Makefile +++ b/arch/mips/boot/dts/mscc/Makefile @@ -1,4 +1,4 @@ # SPDX-License-Identifier: GPL-2.0-only -dtb-$(CONFIG_MSCC_OCELOT) += ocelot_pcb123.dtb ocelot_pcb120.dtb +dtb-$(CONFIG_SOC_VCOREIII) += ocelot_pcb123.dtb ocelot_pcb120.dtb obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y)) |