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| author |   Gregory CLEMENT <gregory.clement@bootlin.com> | 2020-11-10 12:45:08 +0100 |
|---|---|---|
| committer |   Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2020-11-12 23:35:15 +0100 |
| commit | fe0052018a84d50be034449b4175177f569fbf5c (patch) | |
| tree | b7716e6d31d40e47073bdfe3fab306d4026f9441 /arch/mips/boot/dts/mscc/Makefile | |
| parent | MIPS: mscc: Add jaguar2 support (diff) | |
| download | wireguard-linux-fe0052018a84d50be034449b4175177f569fbf5c.tar.xz wireguard-linux-fe0052018a84d50be034449b4175177f569fbf5c.zip | |
MIPS: mscc: Add serval support
Add a device trees and FIT image support for the Microsemi Serval SoC
which belongs to same family of the Ocelot SoC.
It is based on the work of Lars Povlsen <lars.povlsen@microchip.com>.
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to 'arch/mips/boot/dts/mscc/Makefile')
| -rw-r--r-- | arch/mips/boot/dts/mscc/Makefile | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/arch/mips/boot/dts/mscc/Makefile b/arch/mips/boot/dts/mscc/Makefile index befda72ceb26..eeb6b7aae83b 100644 --- a/arch/mips/boot/dts/mscc/Makefile +++ b/arch/mips/boot/dts/mscc/Makefile @@ -5,6 +5,9 @@ dtb-$(CONFIG_SOC_VCOREIII) += \ jaguar2_pcb118.dtb \ luton_pcb091.dtb \ ocelot_pcb120.dtb \ - ocelot_pcb123.dtb + ocelot_pcb123.dtb \ + serval_pcb105.dtb \ + serval_pcb106.dtb + obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y)) |