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| author |   John Crispin <blogic@openwrt.org> | 2011-03-30 09:27:49 +0200 |
|---|---|---|
| committer |   Ralf Baechle <ralf@linux-mips.org> | 2011-05-19 09:55:42 +0100 |
| commit | e47d488935ed0b2dd3d59d3ba4e13956ff6849c0 (patch) | |
| tree | d6cdd24c6fa6d5cf4b5c461a8cc031cf9f3f1014 /arch/mips/pci/Makefile | |
| parent | MIPS: Lantiq: add SoC specific code for XWAY family (diff) | |
| download | wireguard-linux-e47d488935ed0b2dd3d59d3ba4e13956ff6849c0.tar.xz wireguard-linux-e47d488935ed0b2dd3d59d3ba4e13956ff6849c0.zip | |
MIPS: Lantiq: Add PCI controller support.
The Lantiq family of SoCs have a EBU (External Bus Unit). This patch adds
the driver that allows us to use the EBU as a PCI controller. In order for
PCI to work the EBU is set to endianess swap all the data. In addition we
need to make use of SWAP_IO_SPACE for device->host DMA to work.
The clock of the PCI works in several modes (internal/external). If this
is not configured correctly the SoC will hang.
Signed-off-by: John Crispin <blogic@openwrt.org>
Signed-off-by: Ralph Hempel <ralph.hempel@lantiq.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2250/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/pci/Makefile')
| -rw-r--r-- | arch/mips/pci/Makefile | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile index f0d5329289d1..4df879937446 100644 --- a/arch/mips/pci/Makefile +++ b/arch/mips/pci/Makefile @@ -41,6 +41,7 @@ obj-$(CONFIG_SIBYTE_SB1250) += fixup-sb1250.o pci-sb1250.o obj-$(CONFIG_SIBYTE_BCM112X) += fixup-sb1250.o pci-sb1250.o obj-$(CONFIG_SIBYTE_BCM1x80) += pci-bcm1480.o pci-bcm1480ht.o obj-$(CONFIG_SNI_RM) += fixup-sni.o ops-sni.o +obj-$(CONFIG_SOC_XWAY) += pci-lantiq.o ops-lantiq.o obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o obj-$(CONFIG_TANBAC_TB0287) += fixup-tb0287.o |