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authorThomas Gleixner <tglx@linutronix.de>2020-06-11 15:17:57 +0200
committerThomas Gleixner <tglx@linutronix.de>2020-06-11 15:17:57 +0200
commitf77d26a9fc525286bcef3d4f98b52e17482cf49c (patch)
tree6b179c9aa84787773cb601a14a64255e2912154b /arch/openrisc/mm/tlb.c
parentEDAC/amd64: Add AMD family 17h model 60h PCI IDs (diff)
parentx86/entry: Unbreak __irqentry_text_start/end magic (diff)
downloadwireguard-linux-f77d26a9fc525286bcef3d4f98b52e17482cf49c.tar.xz
wireguard-linux-f77d26a9fc525286bcef3d4f98b52e17482cf49c.zip
Merge branch 'x86/entry' into ras/core
to fixup conflicts in arch/x86/kernel/cpu/mce/core.c so MCE specific follow up patches can be applied without creating a horrible merge conflict afterwards.
Diffstat (limited to 'arch/openrisc/mm/tlb.c')
-rw-r--r--arch/openrisc/mm/tlb.c1
1 files changed, 0 insertions, 1 deletions
diff --git a/arch/openrisc/mm/tlb.c b/arch/openrisc/mm/tlb.c
index dd4f2007f7c9..4b680aed8f5f 100644
--- a/arch/openrisc/mm/tlb.c
+++ b/arch/openrisc/mm/tlb.c
@@ -23,7 +23,6 @@
#include <linux/init.h>
#include <asm/tlbflush.h>
-#include <asm/pgtable.h>
#include <asm/mmu_context.h>
#include <asm/spr_defs.h>