diff options
| author |   Jack Miller <jack@codezen.org> | 2016-06-09 12:31:09 +1000 |
|---|---|---|
| committer |   Michael Ellerman <mpe@ellerman.id.au> | 2016-06-21 15:30:50 +1000 |
| commit | bd3ea317fddfd0f2044f94bed294b90c4bc8e69e (patch) | |
| tree | 051da254ea09ce51759123472fbcc52002c0ad53 /arch/powerpc/include/asm/processor.h | |
| parent | powerpc: Improve FSCR init and context switching (diff) | |
| download | wireguard-linux-bd3ea317fddfd0f2044f94bed294b90c4bc8e69e.tar.xz wireguard-linux-bd3ea317fddfd0f2044f94bed294b90c4bc8e69e.zip | |
powerpc: Load Monitor Register Support
This enables new registers, LMRR and LMSER, that can trigger an EBB in
userspace code when a monitored load (via the new ldmx instruction)
loads memory from a monitored space. This facility is controlled by a
new FSCR bit, LM.
This patch disables the FSCR LM control bit on task init and enables
that bit when a load monitor facility unavailable exception is taken
for using it. On context switch, this bit is then used to determine
whether the two relevant registers are saved and restored. This is
done lazily for performance reasons.
Signed-off-by: Jack Miller <jack@codezen.org>
Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Diffstat (limited to 'arch/powerpc/include/asm/processor.h')
| -rw-r--r-- | arch/powerpc/include/asm/processor.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index f6b1a5f51d05..b5925d5d4985 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -314,6 +314,8 @@ struct thread_struct { unsigned long mmcr2; unsigned mmcr0; unsigned used_ebb; + unsigned long lmrr; + unsigned long lmser; #endif }; |