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| author |   Nicholas Piggin <npiggin@gmail.com> | 2020-11-06 14:53:40 +1000 |
|---|---|---|
| committer |   Michael Ellerman <mpe@ellerman.id.au> | 2020-12-09 23:48:14 +1100 |
| commit | e89a8ca94bf583f2577fe722483f0304b3390aa2 (patch) | |
| tree | 68704f0dd295e79396af283b9a9777ade65ac1aa /arch/powerpc/kernel/head_64.S | |
| parent | powerpc/64s/iommu: Don't use atomic_ function on atomic64_t type (diff) | |
| download | wireguard-linux-e89a8ca94bf583f2577fe722483f0304b3390aa2.tar.xz wireguard-linux-e89a8ca94bf583f2577fe722483f0304b3390aa2.zip | |
powerpc/64s: Remove MSR[ISF] bit
No supported processor implements this mode. Setting the bit in
MSR values can be a bit confusing (and would prevent the bit from
ever being reused). Remove it.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20201106045340.1935841-1-npiggin@gmail.com
Diffstat (limited to 'arch/powerpc/kernel/head_64.S')
| -rw-r--r-- | arch/powerpc/kernel/head_64.S | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/arch/powerpc/kernel/head_64.S b/arch/powerpc/kernel/head_64.S index f63d01c78398..ece7f97bafff 100644 --- a/arch/powerpc/kernel/head_64.S +++ b/arch/powerpc/kernel/head_64.S @@ -870,8 +870,7 @@ enable_64b_mode: oris r11,r11,0x8000 /* CM bit set, we'll set ICM later */ mtmsr r11 #else /* CONFIG_PPC_BOOK3E */ - li r12,(MSR_64BIT | MSR_ISF)@highest - sldi r12,r12,48 + LOAD_REG_IMMEDIATE(r12, MSR_64BIT) or r11,r11,r12 mtmsrd r11 isync |