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authorNicholas Piggin <npiggin@gmail.com>2021-01-11 16:24:08 +1000
committerMichael Ellerman <mpe@ellerman.id.au>2021-01-20 15:58:19 +1100
commit08685be7761d69914f08c3d6211c543a385a5b9c (patch)
tree4ca6766ab8b6d80777e668ffa7c1e9fc51e2d2df /arch/powerpc/kernel/vmlinux.lds.S
parentselftests/powerpc: Only test lwm/stmw on big endian (diff)
downloadwireguard-linux-08685be7761d69914f08c3d6211c543a385a5b9c.tar.xz
wireguard-linux-08685be7761d69914f08c3d6211c543a385a5b9c.zip
powerpc/64s: fix scv entry fallback flush vs interrupt
The L1D flush fallback functions are not recoverable vs interrupts, yet the scv entry flush runs with MSR[EE]=1. This can result in a timer (soft-NMI) or MCE or SRESET interrupt hitting here and overwriting the EXRFI save area, which ends up corrupting userspace registers for scv return. Fix this by disabling RI and EE for the scv entry fallback flush. Fixes: f79643787e0a0 ("powerpc/64s: flush L1D on kernel entry") Cc: stable@vger.kernel.org # 5.9+ which also have flush L1D patch backport Reported-by: Tulio Magno Quites Machado Filho <tuliom@linux.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20210111062408.287092-1-npiggin@gmail.com
Diffstat (limited to 'arch/powerpc/kernel/vmlinux.lds.S')
-rw-r--r--arch/powerpc/kernel/vmlinux.lds.S7
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/powerpc/kernel/vmlinux.lds.S b/arch/powerpc/kernel/vmlinux.lds.S
index 4ab426b8b0e0..72fa3c00229a 100644
--- a/arch/powerpc/kernel/vmlinux.lds.S
+++ b/arch/powerpc/kernel/vmlinux.lds.S
@@ -146,6 +146,13 @@ SECTIONS
}
. = ALIGN(8);
+ __scv_entry_flush_fixup : AT(ADDR(__scv_entry_flush_fixup) - LOAD_OFFSET) {
+ __start___scv_entry_flush_fixup = .;
+ *(__scv_entry_flush_fixup)
+ __stop___scv_entry_flush_fixup = .;
+ }
+
+ . = ALIGN(8);
__stf_exit_barrier_fixup : AT(ADDR(__stf_exit_barrier_fixup) - LOAD_OFFSET) {
__start___stf_exit_barrier_fixup = .;
*(__stf_exit_barrier_fixup)