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author | 2019-04-15 11:14:34 +0200 | |
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committer | 2019-04-25 14:51:10 -0700 | |
commit | e28dcc77e8e84c635675958e531a88d077266698 (patch) | |
tree | eeab3bdccd62dec195f56f32e7187667ac7057c0 /arch/riscv/include/asm/uaccess.h | |
parent | riscv: turn mm_segment_t into a struct (diff) | |
download | wireguard-linux-e28dcc77e8e84c635675958e531a88d077266698.tar.xz wireguard-linux-e28dcc77e8e84c635675958e531a88d077266698.zip |
riscv: remove unreachable big endian code
RISC-V is always little endian.
Signed-off-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'arch/riscv/include/asm/uaccess.h')
-rw-r--r-- | arch/riscv/include/asm/uaccess.h | 9 |
1 files changed, 1 insertions, 8 deletions
diff --git a/arch/riscv/include/asm/uaccess.h b/arch/riscv/include/asm/uaccess.h index c51fc8bfbdde..b26f407be5c8 100644 --- a/arch/riscv/include/asm/uaccess.h +++ b/arch/riscv/include/asm/uaccess.h @@ -101,15 +101,8 @@ static inline int __access_ok(unsigned long addr, unsigned long size) * on our cache or tlb entries. */ -#if defined(__LITTLE_ENDIAN) -#define __MSW 1 #define __LSW 0 -#elif defined(__BIG_ENDIAN) -#define __MSW 0 -#define __LSW 1 -#else -#error "Unknown endianness" -#endif +#define __MSW 1 /* * The "__xxx" versions of the user access functions do not verify the address |