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| author |   Chen Liqin <liqin.chen@sunplusct.com> | 2009-06-12 22:01:00 +0800 |
|---|---|---|
| committer |   Arnd Bergmann <arnd@arndb.de> | 2009-06-19 11:38:47 +0200 |
| commit | 6bc9a3966f0395419b09b2ec90f89f7f00341b37 (patch) | |
| tree | 9c0d9d5376020266f5602501c8376d4a4f13142d /arch/score/include/asm/irq.h | |
| parent | Merge branch 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tytso/ext4 (diff) | |
| download | wireguard-linux-6bc9a3966f0395419b09b2ec90f89f7f00341b37.tar.xz wireguard-linux-6bc9a3966f0395419b09b2ec90f89f7f00341b37.zip | |
score: Add support for Sunplus S+core architecture
This is the complete set of new arch Score's files for linux.
Score instruction set support 16bits, 32bits and 64bits instruction,
Score SOC had been used in game machine and LCD TV.
Signed-off-by: Chen Liqin <liqin.chen@sunplusct.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/score/include/asm/irq.h')
| -rw-r--r-- | arch/score/include/asm/irq.h | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/arch/score/include/asm/irq.h b/arch/score/include/asm/irq.h new file mode 100644 index 000000000000..401f6704848c --- /dev/null +++ b/arch/score/include/asm/irq.h @@ -0,0 +1,33 @@ +#ifndef _ASM_SCORE_IRQ_H +#define _ASM_SCORE_IRQ_H + +#define EXCEPTION_VECTOR_BASE_ADDR 0xa0000000 +#define VECTOR_ADDRESS_OFFSET_MODE4 0 +#define VECTOR_ADDRESS_OFFSET_MODE16 1 + +#define DEBUG_VECTOR_SIZE (0x4) +#define DEBUG_VECTOR_BASE_ADDR ((EXCEPTION_VECTOR_BASE_ADDR) + 0x1fc) + +#define GENERAL_VECTOR_SIZE (0x10) +#define GENERAL_VECTOR_BASE_ADDR ((EXCEPTION_VECTOR_BASE_ADDR) + 0x200) + +#define NR_IRQS 64 +#define IRQ_VECTOR_SIZE (0x10) +#define IRQ_VECTOR_BASE_ADDR ((EXCEPTION_VECTOR_BASE_ADDR) + 0x210) +#define IRQ_VECTOR_END_ADDR ((EXCEPTION_VECTOR_BASE_ADDR) + 0x5f0) + +#define irq_canonicalize(irq) (irq) + +#define P_INT_PNDL 0x95F50000 +#define P_INT_PNDH 0x95F50004 +#define P_INT_PRIORITY_M 0x95F50008 +#define P_INT_PRIORITY_SG0 0x95F50010 +#define P_INT_PRIORITY_SG1 0x95F50014 +#define P_INT_PRIORITY_SG2 0x95F50018 +#define P_INT_PRIORITY_SG3 0x95F5001C +#define P_INT_MASKL 0x95F50020 +#define P_INT_MASKH 0x95F50024 + +#define IRQ_TIMER (7) /* Timer IRQ number of SPCT6600 */ + +#endif /* _ASM_SCORE_IRQ_H */ |