aboutsummaryrefslogtreecommitdiffstatshomepage
path: root/arch/x86/crypto/aesni-intel_asm.S
diff options
context:
space:
mode:
authorHuang Ying <ying.huang@intel.com>2009-11-09 13:52:26 -0500
committerHerbert Xu <herbert@gondor.apana.org.au>2009-11-09 13:52:26 -0500
commitfd650a6394b3242edf125ba9c4d500349a6d7178 (patch)
treefe67f242b739ff5b74a37896a19d1e18430bac1d /arch/x86/crypto/aesni-intel_asm.S
parentcrypto: ghash-intel - Fix irq_fpu_usable usage (diff)
downloadwireguard-linux-fd650a6394b3242edf125ba9c4d500349a6d7178.tar.xz
wireguard-linux-fd650a6394b3242edf125ba9c4d500349a6d7178.zip
x86: Generate .byte code for some new instructions via gas macro
It will take some time for binutils (gas) to support some newly added instructions, such as SSE4.1 instructions or the AES-NI instructions found in upcoming Intel CPU. To make the source code can be compiled by old binutils, .byte code is used instead of the assembly instruction. But the readability and flexibility of raw .byte code is not good. This patch solves the issue of raw .byte code via generating it via assembly instruction like gas macro. The syntax is as close as possible to real assembly instruction. Some helper macros such as MODRM is not a full feature implementation. It can be extended when necessary. Signed-off-by: Huang Ying <ying.huang@intel.com> Acked-by: H. Peter Anvin <hpa@zytor.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Diffstat (limited to 'arch/x86/crypto/aesni-intel_asm.S')
0 files changed, 0 insertions, 0 deletions