diff options
| author |   Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com> | 2017-04-09 15:00:21 -0700 |
|---|---|---|
| committer |   Andy Shevchenko <andriy.shevchenko@linux.intel.com> | 2017-04-28 21:51:28 +0300 |
| commit | 62a7b9c859d09af860c71cfbea4381061975ca72 (patch) | |
| tree | bdf4f62e5313716e8653057b6ab1a2d9a16ed212 /arch/x86/include/asm/intel_pmc_ipc.h | |
| parent | platform/x86: intel_pmc_ipc: Fix iTCO_wdt GCS memory mapping failure (diff) | |
| download | wireguard-linux-62a7b9c859d09af860c71cfbea4381061975ca72.tar.xz wireguard-linux-62a7b9c859d09af860c71cfbea4381061975ca72.zip | |
platform/x86: intel_pmc_ipc: use gcr mem base for S0ix counter read
To maintain the uniformity in accessing GCR registers, this patch
modifies the S0ix counter read function to use GCR address base
instead of ipc address base.
Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
Reviewed-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
Tested-by: Shanth Murthy <shanth.murthy@intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Diffstat (limited to 'arch/x86/include/asm/intel_pmc_ipc.h')
| -rw-r--r-- | arch/x86/include/asm/intel_pmc_ipc.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/x86/include/asm/intel_pmc_ipc.h b/arch/x86/include/asm/intel_pmc_ipc.h index 8402efef10ad..fac89eb78a6b 100644 --- a/arch/x86/include/asm/intel_pmc_ipc.h +++ b/arch/x86/include/asm/intel_pmc_ipc.h @@ -25,6 +25,8 @@ /* GCR reg offsets from gcr base*/ #define PMC_GCR_PMC_CFG_REG 0x08 +#define PMC_GCR_TELEM_DEEP_S0IX_REG 0x78 +#define PMC_GCR_TELEM_SHLW_S0IX_REG 0x80 #if IS_ENABLED(CONFIG_INTEL_PMC_IPC) |