diff options
| author |   Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> | 2022-05-19 05:27:03 -0500 |
|---|---|---|
| committer |   Paolo Bonzini <pbonzini@redhat.com> | 2022-06-24 12:50:35 -0400 |
| commit | 4d1d7942e36add0aa741a62d0c8e3aba2d5b3ab1 (patch) | |
| tree | e91064793b187eeea8feaf28d053dec2855eb007 /arch/x86/include/asm/svm.h | |
| parent | KVM: x86: nSVM: always intercept x2apic msrs (diff) | |
| download | wireguard-linux-4d1d7942e36add0aa741a62d0c8e3aba2d5b3ab1.tar.xz wireguard-linux-4d1d7942e36add0aa741a62d0c8e3aba2d5b3ab1.zip | |
KVM: SVM: Introduce logic to (de)activate x2AVIC mode
Introduce logic to (de)activate AVIC, which also allows
switching between AVIC to x2AVIC mode at runtime.
When an AVIC-enabled guest switches from APIC to x2APIC mode,
the SVM driver needs to perform the following steps:
1. Set the x2APIC mode bit for AVIC in VMCB along with the maximum
APIC ID support for each mode accodingly.
2. Disable x2APIC MSRs interception in order to allow the hardware
to virtualize x2APIC MSRs accesses.
Reported-by: kernel test robot <lkp@intel.com>
Reviewed-by: Maxim Levitsky <mlevitsk@redhat.com>
Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Message-Id: <20220519102709.24125-12-suravee.suthikulpanit@amd.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'arch/x86/include/asm/svm.h')
| -rw-r--r-- | arch/x86/include/asm/svm.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/x86/include/asm/svm.h b/arch/x86/include/asm/svm.h index ed4b83d7f09e..0361626841bc 100644 --- a/arch/x86/include/asm/svm.h +++ b/arch/x86/include/asm/svm.h @@ -256,6 +256,7 @@ enum avic_ipi_failure_cause { AVIC_IPI_FAILURE_INVALID_BACKING_PAGE, }; +#define AVIC_PHYSICAL_MAX_INDEX_MASK GENMASK_ULL(9, 0) /* * For AVIC, the max index allowed for physical APIC ID |