diff options
| author |   James Morse <james.morse@arm.com> | 2020-07-08 16:39:27 +0000 |
|---|---|---|
| committer |   Borislav Petkov <bp@suse.de> | 2020-08-19 09:38:57 +0200 |
| commit | 5df3ca9334d5603e4afbb95953d0affb37dcf86b (patch) | |
| tree | 59d5f906af1d0058e4ca919be1004b6cf67dba7a /arch/x86/kernel/cpu/resctrl/core.c | |
| parent | x86/resctrl: Add struct rdt_membw::arch_needs_linear to explain AMD/Intel MBA difference (diff) | |
| download | wireguard-linux-5df3ca9334d5603e4afbb95953d0affb37dcf86b.tar.xz wireguard-linux-5df3ca9334d5603e4afbb95953d0affb37dcf86b.zip | |
x86/resctrl: Merge AMD/Intel parse_bw() calls
Now after arch_needs_linear has been added, the parse_bw() calls are
almost the same between AMD and Intel.
The difference is '!is_mba_sc()', which is not checked on AMD. This
will always be true on AMD CPUs as mba_sc cannot be enabled as
is_mba_linear() is false.
Removing this duplication means user-space visible behaviour and
error messages are not validated or generated in different places.
Reviewed-by : Babu Moger <babu.moger@amd.com>
Signed-off-by: James Morse <james.morse@arm.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Reviewed-by: Reinette Chatre <reinette.chatre@intel.com>
Link: https://lkml.kernel.org/r/20200708163929.2783-9-james.morse@arm.com
Diffstat (limited to 'arch/x86/kernel/cpu/resctrl/core.c')
| -rw-r--r-- | arch/x86/kernel/cpu/resctrl/core.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resctrl/core.c index 52b8991de8a3..10a52d173e4f 100644 --- a/arch/x86/kernel/cpu/resctrl/core.c +++ b/arch/x86/kernel/cpu/resctrl/core.c @@ -168,6 +168,7 @@ struct rdt_resource rdt_resources_all[] = { .name = "MB", .domains = domain_init(RDT_RESOURCE_MBA), .cache_level = 3, + .parse_ctrlval = parse_bw, .format_str = "%d=%*u", .fflags = RFTYPE_RES_MB, }, @@ -926,7 +927,6 @@ static __init void rdt_init_res_defs_intel(void) else if (r->rid == RDT_RESOURCE_MBA) { r->msr_base = MSR_IA32_MBA_THRTL_BASE; r->msr_update = mba_wrmsr_intel; - r->parse_ctrlval = parse_bw_intel; } } } @@ -946,7 +946,6 @@ static __init void rdt_init_res_defs_amd(void) else if (r->rid == RDT_RESOURCE_MBA) { r->msr_base = MSR_IA32_MBA_BW_BASE; r->msr_update = mba_wrmsr_amd; - r->parse_ctrlval = parse_bw_amd; } } } |