diff options
| author |   Ingo Molnar <mingo@kernel.org> | 2017-07-01 10:39:25 +0200 |
|---|---|---|
| committer | Ingo Molnar <mingo@kernel.org> | 2017-07-01 10:39:25 +0200 |
| commit | 23acd3e1a0a377cf3730ccb753aa1fdc50378396 (patch) | |
| tree | a80d7cfd2be43d77af659d5f309a5032be5e0662 /arch/x86 | |
| parent | perf/x86/intel: Constify the 'lbr_desc[]' array and make a function static (diff) | |
| parent | perf auxtrace: Add CPU filter support (diff) | |
| download | wireguard-linux-23acd3e1a0a377cf3730ccb753aa1fdc50378396.tar.xz wireguard-linux-23acd3e1a0a377cf3730ccb753aa1fdc50378396.zip | |
Merge tag 'perf-core-for-mingo-4.13-20170630' of git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux into perf/core
Pull perf/core improvements and fixes from Arnaldo Carvalho de Melo:
Intel PT enhancements:
- Support "ptwrite" instruction, a way to stuff 32 or 64 bit values into
the Intel PT trace (Adrian Hunter)
- Support power events in Intel PT to report changes to C-state (Adrian
Hunter)
- Synthesize Intel PT events as PERF_RECORD_SAMPLE records with a
perf_event_attr.type (PERF_TYPE_SYNTH) just after the range used by the
kernel, i.e. right after what is allocated for PMUs, at INT_MAX + 1U,
attr.config will have the identification for the synthesized event and
the PERF_SAMPLE_RAW payload will have its fields (Adrian Hunter)
Infrastructure changes:
- Remove warning() and error(), using instead pr_warning() and
pr_error(), consolidating error reporting (Arnaldo Carvalho de Melo)
- Add platform dependency to 'perf test 15' (Thomas Richter)
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Diffstat (limited to 'arch/x86')
| -rw-r--r-- | arch/x86/lib/x86-opcode-map.txt | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/x86/lib/x86-opcode-map.txt b/arch/x86/lib/x86-opcode-map.txt index 767be7c76034..12e377184ee4 100644 --- a/arch/x86/lib/x86-opcode-map.txt +++ b/arch/x86/lib/x86-opcode-map.txt @@ -1009,7 +1009,7 @@ GrpTable: Grp15 1: fxstor | RDGSBASE Ry (F3),(11B) 2: vldmxcsr Md (v1) | WRFSBASE Ry (F3),(11B) 3: vstmxcsr Md (v1) | WRGSBASE Ry (F3),(11B) -4: XSAVE +4: XSAVE | ptwrite Ey (F3),(11B) 5: XRSTOR | lfence (11B) 6: XSAVEOPT | clwb (66) | mfence (11B) 7: clflush | clflushopt (66) | sfence (11B) |