diff options
| author |   Matt Redfearn <matt.redfearn@imgtec.com> | 2016-05-18 17:12:36 +0100 |
|---|---|---|
| committer |   Ralf Baechle <ralf@linux-mips.org> | 2016-05-28 12:35:05 +0200 |
| commit | 63a8802f4fb60963d3f91b072f4d0424330ec0d4 (patch) | |
| tree | 5003df7cbee637eed4e4f2302ffe97c917967bc2 /arch | |
| parent | MIPS: Add definitions of SegCtl registers and use them (diff) | |
| download | wireguard-linux-63a8802f4fb60963d3f91b072f4d0424330ec0d4.tar.xz wireguard-linux-63a8802f4fb60963d3f91b072f4d0424330ec0d4.zip | |
MIPS: CPS: Copy EVA configuration when starting secondary VPs.
When starting secondary VPEs which support EVA and the SegCtl registers,
copy the memory segmentation configuration from the running VPE to ensure
that all VPEs in the core have a consistent virtual memory map.
The EVA configuration of secondary cores is dealt with when starting the
core via the CM.
Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/13291/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/mips/kernel/cps-vec.S | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/arch/mips/kernel/cps-vec.S b/arch/mips/kernel/cps-vec.S index 51b98dc371b3..59476a607add 100644 --- a/arch/mips/kernel/cps-vec.S +++ b/arch/mips/kernel/cps-vec.S @@ -441,6 +441,21 @@ LEAF(mips_cps_boot_vpes) mfc0 t0, CP0_CONFIG mttc0 t0, CP0_CONFIG + /* + * Copy the EVA config from this VPE if the CPU supports it. + * CONFIG3 must exist to be running MT startup - just read it. + */ + mfc0 t0, CP0_CONFIG, 3 + and t0, t0, MIPS_CONF3_SC + beqz t0, 3f + nop + mfc0 t0, CP0_SEGCTL0 + mttc0 t0, CP0_SEGCTL0 + mfc0 t0, CP0_SEGCTL1 + mttc0 t0, CP0_SEGCTL1 + mfc0 t0, CP0_SEGCTL2 + mttc0 t0, CP0_SEGCTL2 +3: /* Ensure no software interrupts are pending */ mttc0 zero, CP0_CAUSE mttc0 zero, CP0_STATUS |