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| author |   Paul Burton <paul.burton@imgtec.com> | 2016-05-17 15:31:04 +0100 |
|---|---|---|
| committer |   Ralf Baechle <ralf@linux-mips.org> | 2016-05-28 12:35:02 +0200 |
| commit | 640356a48750ff9ef3303d85158ef9c42c3a18b6 (patch) | |
| tree | 156b010b5d2c78df6048993a9dd6284f17bf65d7 /arch | |
| parent | MIPS: pic32mzda: fix getting timer clock rate. (diff) | |
| download | wireguard-linux-640356a48750ff9ef3303d85158ef9c42c3a18b6.tar.xz wireguard-linux-640356a48750ff9ef3303d85158ef9c42c3a18b6.zip | |
MIPS: Clear Status IPL field when using EIC
When using an external interrupt controller (EIC) the interrupt mask
bits in the cop0 Status register are reused for the Interrupt Priority
Level, and any interrupts with a priority lower than the field will be
ignored. Clear the field to 0 by default such that all interrupts are
serviced. Without doing so we default to arbitrarily ignoring all or
some subset of interrupts.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Reviewed-by: Matt Redfearn <matt.redfearn@imgtec.com>
Tested-by: Matt Redfearn <matt.redfearn@imgtec.com>
Cc: Guenter Roeck <linux@roeck-us.net>
Cc: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Cc: Joe Perches <joe@perches.com>
Cc: James Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/13272/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/mips/kernel/irq.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/mips/kernel/irq.c b/arch/mips/kernel/irq.c index 8eb5af805964..f25f7eab7307 100644 --- a/arch/mips/kernel/irq.c +++ b/arch/mips/kernel/irq.c @@ -54,6 +54,9 @@ void __init init_IRQ(void) for (i = 0; i < NR_IRQS; i++) irq_set_noprobe(i); + if (cpu_has_veic) + clear_c0_status(ST0_IM); + arch_init_irq(); } |