diff options
| author |   Anup Patel <anup.patel@wdc.com> | 2020-04-24 10:29:28 +0530 |
|---|---|---|
| committer |   Palmer Dabbelt <palmerdabbelt@google.com> | 2020-05-04 14:09:00 -0700 |
| commit | a2da5b181f888b3cdb4727b6c60a8755cedce272 (patch) | |
| tree | a130ad2abc6df83f91e3dc28b91c79ad7262ff51 /arch | |
| parent | RISC-V: Add bitmap reprensenting ISA features common across CPUs (diff) | |
| download | wireguard-linux-a2da5b181f888b3cdb4727b6c60a8755cedce272.tar.xz wireguard-linux-a2da5b181f888b3cdb4727b6c60a8755cedce272.zip | |
RISC-V: Remove N-extension related defines
The RISC-V N-extension is still in draft state hence remove
N-extension related defines from asm/csr.h.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/riscv/include/asm/csr.h | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 8e18d2c64399..cec462e198ce 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -51,13 +51,10 @@ #define CAUSE_IRQ_FLAG (_AC(1, UL) << (__riscv_xlen - 1)) /* Interrupt causes (minus the high bit) */ -#define IRQ_U_SOFT 0 #define IRQ_S_SOFT 1 #define IRQ_M_SOFT 3 -#define IRQ_U_TIMER 4 #define IRQ_S_TIMER 5 #define IRQ_M_TIMER 7 -#define IRQ_U_EXT 8 #define IRQ_S_EXT 9 #define IRQ_M_EXT 11 |