diff options
| author |   Huang Pei <huangpei@loongson.cn> | 2020-09-01 14:53:09 +0800 |
|---|---|---|
| committer |   Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2020-09-03 12:00:03 +0200 |
| commit | bb06748207cfb1502d11b90325eba7f8c44c9f02 (patch) | |
| tree | 71e7c8aa6a0d3ac586befa5c3b23398aa7ce809d /arch | |
| parent | MIPS: perf: Fix wrong check condition of Loongson event IDs (diff) | |
| download | wireguard-linux-bb06748207cfb1502d11b90325eba7f8c44c9f02.tar.xz wireguard-linux-bb06748207cfb1502d11b90325eba7f8c44c9f02.zip | |
MIPS: add missing MSACSR and upper MSA initialization
In cc97ab235f3f ("MIPS: Simplify FP context initialization), init_fp_ctx
just initialize the fp/msa context, and own_fp_inatomic just restore
FCSR and 64bit FP regs from it, but miss MSACSR and upper MSA regs for
MSA, so MSACSR and MSA upper regs's value from previous task on current
cpu can leak into current task and cause unpredictable behavior when MSA
context not initialized.
Fixes: cc97ab235f3f ("MIPS: Simplify FP context initialization")
Signed-off-by: Huang Pei <huangpei@loongson.cn>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/mips/kernel/traps.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 38aa07ccdbcc..cf788591f091 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -1287,6 +1287,18 @@ static int enable_restore_fp_context(int msa) err = own_fpu_inatomic(1); if (msa && !err) { enable_msa(); + /* + * with MSA enabled, userspace can see MSACSR + * and MSA regs, but the values in them are from + * other task before current task, restore them + * from saved fp/msa context + */ + write_msa_csr(current->thread.fpu.msacsr); + /* + * own_fpu_inatomic(1) just restore low 64bit, + * fix the high 64bit + */ + init_msa_upper(); set_thread_flag(TIF_USEDMSA); set_thread_flag(TIF_MSA_CTX_LIVE); } |