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| author |   Jeffrey Hugo <jhugo@codeaurora.org> | 2020-05-01 00:35:53 +0530 |
|---|---|---|
| committer |   Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2020-05-05 16:58:35 +0200 |
| commit | 45723a44845c90c8e859fd0e2b0bb492322b5d0b (patch) | |
| tree | b9fd0cfdff20f193b82fa010fbb41d70eea0304b /drivers/bus/mhi/core/internal.h | |
| parent | bus: mhi: core: Remove link_status() callback (diff) | |
| download | wireguard-linux-45723a44845c90c8e859fd0e2b0bb492322b5d0b.tar.xz wireguard-linux-45723a44845c90c8e859fd0e2b0bb492322b5d0b.zip | |
bus: mhi: core: Offload register accesses to the controller
When reading or writing MHI registers, the core assumes that the physical
link is a memory mapped PCI link. This assumption may not hold for all
MHI devices. The controller knows what is the physical link (ie PCI, I2C,
SPI, etc), and therefore knows the proper methods to access that link.
The controller can also handle link specific error scenarios, such as
reading -1 when the PCI link went down.
Therefore, it is appropriate that the MHI core requests the controller to
make register accesses on behalf of the core, which abstracts the core
from link specifics, and end up removing an unnecessary assumption.
Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org>
Reviewed-by: Hemant Kumar <hemantk@codeaurora.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20200430190555.32741-5-manivannan.sadhasivam@linaro.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/bus/mhi/core/internal.h')
| -rw-r--r-- | drivers/bus/mhi/core/internal.h | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/drivers/bus/mhi/core/internal.h b/drivers/bus/mhi/core/internal.h index 5deadfaa053a..095d95bc0e37 100644 --- a/drivers/bus/mhi/core/internal.h +++ b/drivers/bus/mhi/core/internal.h @@ -11,9 +11,6 @@ extern struct bus_type mhi_bus_type; -/* MHI MMIO register mapping */ -#define PCI_INVALID_READ(val) (val == U32_MAX) - #define MHIREGLEN (0x0) #define MHIREGLEN_MHIREGLEN_MASK (0xFFFFFFFF) #define MHIREGLEN_MHIREGLEN_SHIFT (0) |