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authorSamuel Holland <samuel.holland@sifive.com>2023-07-24 17:42:47 -0700
committerStephen Boyd <sboyd@kernel.org>2023-10-23 20:26:49 -0700
commitee58d6a115cefd7e8065eb469788dafa00b999d1 (patch)
treed09a8f113927a8a710d11655d9a7ae87d4b38beb /drivers/clk/analogbits
parentLinux 6.6-rc1 (diff)
downloadwireguard-linux-ee58d6a115cefd7e8065eb469788dafa00b999d1.tar.xz
wireguard-linux-ee58d6a115cefd7e8065eb469788dafa00b999d1.zip
clk: analogbits: Allow building the library as a module
This library is only used by the SiFive PRCI driver. When that driver is built as a module, it makes sense to build this library as a module too. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Link: https://lore.kernel.org/r/20230725004248.381868-1-samuel.holland@sifive.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/analogbits')
-rw-r--r--drivers/clk/analogbits/Kconfig2
-rw-r--r--drivers/clk/analogbits/wrpll-cln28hpc.c8
2 files changed, 9 insertions, 1 deletions
diff --git a/drivers/clk/analogbits/Kconfig b/drivers/clk/analogbits/Kconfig
index 1e291b185438..7d73db0fcd49 100644
--- a/drivers/clk/analogbits/Kconfig
+++ b/drivers/clk/analogbits/Kconfig
@@ -1,3 +1,3 @@
# SPDX-License-Identifier: GPL-2.0-only
config CLK_ANALOGBITS_WRPLL_CLN28HPC
- bool
+ tristate
diff --git a/drivers/clk/analogbits/wrpll-cln28hpc.c b/drivers/clk/analogbits/wrpll-cln28hpc.c
index 09ca82356399..65d422a588e1 100644
--- a/drivers/clk/analogbits/wrpll-cln28hpc.c
+++ b/drivers/clk/analogbits/wrpll-cln28hpc.c
@@ -28,6 +28,7 @@
#include <linux/math64.h>
#include <linux/math.h>
#include <linux/minmax.h>
+#include <linux/module.h>
#include <linux/clk/analogbits-wrpll-cln28hpc.h>
@@ -312,6 +313,7 @@ int wrpll_configure_for_rate(struct wrpll_cfg *c, u32 target_rate,
return 0;
}
+EXPORT_SYMBOL_GPL(wrpll_configure_for_rate);
/**
* wrpll_calc_output_rate() - calculate the PLL's target output rate
@@ -349,6 +351,7 @@ unsigned long wrpll_calc_output_rate(const struct wrpll_cfg *c,
return n;
}
+EXPORT_SYMBOL_GPL(wrpll_calc_output_rate);
/**
* wrpll_calc_max_lock_us() - return the time for the PLL to lock
@@ -366,3 +369,8 @@ unsigned int wrpll_calc_max_lock_us(const struct wrpll_cfg *c)
{
return MAX_LOCK_US;
}
+EXPORT_SYMBOL_GPL(wrpll_calc_max_lock_us);
+
+MODULE_AUTHOR("Paul Walmsley <paul.walmsley@sifive.com>");
+MODULE_DESCRIPTION("Analog Bits Wide-Range PLL library");
+MODULE_LICENSE("GPL");