diff options
| author |   Claudiu Beznea <claudiu.beznea@microchip.com> | 2021-10-11 14:27:16 +0300 |
|---|---|---|
| committer |   Stephen Boyd <sboyd@kernel.org> | 2021-10-26 18:27:43 -0700 |
| commit | 7029db09b2025f863f191b3d5b1d7859a5e26a8d (patch) | |
| tree | be34cc047ce7069e9c4d39c032cc469f760fd646 /drivers/clk/at91/at91sam9g45.c | |
| parent | clk: at91: clk-sam9x60-pll: add notifier for div part of PLL (diff) | |
| download | wireguard-linux-7029db09b2025f863f191b3d5b1d7859a5e26a8d.tar.xz wireguard-linux-7029db09b2025f863f191b3d5b1d7859a5e26a8d.zip | |
clk: at91: clk-master: add notifier for divider
SAMA7G5 supports DVFS by changing cpuck. On SAMA7G5 mck0 shares the same
parent with cpuck as seen in the following clock tree:
+----------> cpuck
|
FRAC PLL ---> DIV PLL -+-> DIV ---> mck0
mck0 could go b/w 32KHz and 200MHz on SAMA7G5. To avoid mck0 overclocking
while changing FRAC PLL or DIV PLL the commit implements a notifier for
mck0 which applies a safe divider to register (maximum value of the divider
which is 5) on PRE_RATE_CHANGE events (such that changes on PLL to not
overclock mck0) and sets the maximum allowed rate on POST_RATE_CHANGE
events.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20211011112719.3951784-13-claudiu.beznea@microchip.com
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/at91/at91sam9g45.c')
| -rw-r--r-- | drivers/clk/at91/at91sam9g45.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/at91/at91sam9g45.c b/drivers/clk/at91/at91sam9g45.c index 15da0dfe3ef2..7ed984f8058c 100644 --- a/drivers/clk/at91/at91sam9g45.c +++ b/drivers/clk/at91/at91sam9g45.c @@ -164,7 +164,7 @@ static void __init at91sam9g45_pmc_setup(struct device_node *np) &at91rm9200_master_layout, &mck_characteristics, &at91sam9g45_mck_lock, - CLK_SET_RATE_GATE); + CLK_SET_RATE_GATE, 0); if (IS_ERR(hw)) goto err_free; |