diff options
| author |   Claudiu Beznea <claudiu.beznea@microchip.com> | 2020-11-19 17:43:12 +0200 |
|---|---|---|
| committer |   Stephen Boyd <sboyd@kernel.org> | 2020-12-19 11:50:55 -0800 |
| commit | 8dc4af8bef127425271e06d09370a2479dae69c3 (patch) | |
| tree | 63114c00b05016b1744a70d8380db17e0e911087 /drivers/clk/at91/pmc.h | |
| parent | clk: at91: sama7g5: add 5th divisor for mck0 layout and characteristics (diff) | |
| download | wireguard-linux-8dc4af8bef127425271e06d09370a2479dae69c3.tar.xz wireguard-linux-8dc4af8bef127425271e06d09370a2479dae69c3.zip | |
clk: at91: clk-sam9x60-pll: allow runtime changes for pll
Allow runtime frequency changes for PLLs registered with proper flags.
This is necessary for CPU PLL on SAMA7G5 which is used by DVFS.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/1605800597-16720-7-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/at91/pmc.h')
| -rw-r--r-- | drivers/clk/at91/pmc.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h index 0a9364bde339..bedcd85ad750 100644 --- a/drivers/clk/at91/pmc.h +++ b/drivers/clk/at91/pmc.h @@ -190,14 +190,14 @@ struct clk_hw * __init sam9x60_clk_register_div_pll(struct regmap *regmap, spinlock_t *lock, const char *name, const char *parent_name, u8 id, const struct clk_pll_characteristics *characteristics, - const struct clk_pll_layout *layout, bool critical); + const struct clk_pll_layout *layout, u32 flags); struct clk_hw * __init sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock, const char *name, const char *parent_name, struct clk_hw *parent_hw, u8 id, const struct clk_pll_characteristics *characteristics, - const struct clk_pll_layout *layout, bool critical); + const struct clk_pll_layout *layout, u32 flags); struct clk_hw * __init at91_clk_register_programmable(struct regmap *regmap, const char *name, |