Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk updates from Stephen Boyd:
 "This merge window we have one small clk provider API in the core
  framework and then a bunch of driver updates and a handful of new
  drivers. In terms of diffstat the Qualcomm and Amlogic drivers are
  high up there because of all the clk data introcued by new drivers.
  The Nvidia Tegra driver had a lot of work done this cycle too to
  support suspend/resume and memory controllers. And the OMAP clk driver
  got proper clk and reset handling in place.

  Rounding out the patches are various updates to remove unused data,
  mark things static, correct incorrect data in drivers, etc. All the
  little things that improve drivers and maintain code health. I will
  point out that there's a patch in here for the GPIO clk driver, that
  almost nobody uses, which changes behavior and causes clk_set_rate()
  to try to change the GPIO gate clk's parent. Other than that things
  are fairly well SoC specific here.

  Core:
   - Add a clk provider API to get current parent index
   - Plug a memory leak in clk_unregister() path

  New Drivers:
   - CGU in Ingenix X1000
   - Bitmain BM1880 clks
   - Qualcomm MSM8998 GPU clk controllers
   - Qualcomm SC7180 GCC and RPMH clk controllers
   - Qualcomm QCS404 Q6SSTOP clk controllers
   - Add support for the Renesas R-Car M3-W+ (r8a77961) SoC
   - Add support for the Renesas RZ/G2N (r8a774b1) SoC
   - Add Tegra20/30 External Memory Clock (EMC) support

  Updates:
   - Make gpio gate clks propagate rate setting up to parent
   - Prepare Armada 3700 for suspend to RAM by moving PCIe
     suspend/resume priority
   - Drop unused variables, enums, etc. in various clk drivers
   - Convert various drivers to use devm_platform_ioremap_resource()
   - Use struct_size() some more in various clk drivers
   - Improve Rockchip px30 clk tree
   - Add suspend/resume support to Tegra210 clk driver
   - Reimplement SOR clks on earlier Tegra SoCs, helping HDMI and DP
   - Allwinner DT exports and H6 clk tree fixes
   - Proper clk and reset handling for OMAP SoCs
   - Revamped TI divider clk to clamp max divider
   - Make 1443X/1416X PLL clock structure common for reusing among i.MX8
     SoCs
   - Drop IMX7ULP_CLK_MIPI_PLL clock, it shouldn't be used
   - Add VIDEO2_PLL clock for imx8mq
   - Add missing gate clock for pll1/2 fixed dividers on i.MX8 SoCs
   - Add sm1 support in the Amlogic audio clock controller
   - Switch some clocks on R-Car Gen2/3 to .determine_rate()
   - Remove Renesas R-Car Gen2 legacy DT clock support
   - Improve arithmetic divisions on Renesas R-Car Gen2 and Gen3
   - Improve Renesas R-Car Gen3 SD clock handling
   - Add rate table for Samsung exynos542x GPU and VPLL clks
   - Fix potential CPU performance degradation after system
     suspend/resume cycle on exynos542x SoCs"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (160 commits)
  clk: aspeed: Add RMII RCLK gates for both AST2500 MACs
  MAINTAINERS: Add entry for BM1880 SoC clock driver
  clk: Add common clock driver for BM1880 SoC
  dt-bindings: clock: Add devicetree binding for BM1880 SoC
  clk: Add clk_hw_unregister_composite helper function definition
  clk: Zero init clk_init_data in helpers
  clk: ingenic: Allow drivers to be built with COMPILE_TEST
  MAINTAINERS: Update section for Ux500 clock drivers
  clk: mark clk_disable_unused() as __init
  clk: Fix memory leak in clk_unregister()
  clk: Ingenic: Add CGU driver for X1000.
  dt-bindings: clock: Add X1000 bindings.
  clk: tegra: Use match_string() helper to simplify the code
  clk: pxa: fix one of the pxa RTC clocks
  clk: sprd: Use IS_ERR() to validate the return value of syscon_regmap_lookup_by_phandle()
  clk: armada-xp: remove unused code
  clk: tegra: Fix build error without CONFIG_PM_SLEEP
  clk: tegra: Add missing stubs for the case of !CONFIG_PM_SLEEP
  clk: tegra: Optimize PLLX restore on Tegra20/30
  clk: tegra: Add suspend and resume support on Tegra210
  ...

1 files changed, 46 insertions, 3 deletions

diff --git a/drivers/clk/clk-ast2600.c b/drivers/clk/clk-ast2600.c
index b1318e6b655b..392d01705b97 100644
--- a/drivers/clk/clk-ast2600.c
+++ b/drivers/clk/clk-ast2600.c
@@ -15,7 +15,7 @@
 
 #include "clk-aspeed.h"
 
-#define ASPEED_G6_NUM_CLKS		67
+#define ASPEED_G6_NUM_CLKS		71
 
 #define ASPEED_G6_SILICON_REV		0x004
 
@@ -40,6 +40,9 @@
 
 #define ASPEED_G6_STRAP1		0x500
 
+#define ASPEED_MAC12_CLK_DLY		0x340
+#define ASPEED_MAC34_CLK_DLY		0x350
+
 /* Globally visible clocks */
 static DEFINE_SPINLOCK(aspeed_g6_clk_lock);
 
@@ -116,8 +119,6 @@ static const struct aspeed_gate_data aspeed_g6_gates[] = {
 	[ASPEED_CLK_GATE_FSICLK]	= { 62,  59, "fsiclk-gate",	NULL,	 0 },	/* FSI */
 };
 
-static const char * const eclk_parent_names[] = { "mpll", "hpll", "dpll" };
-
 static const struct clk_div_table ast2600_eclk_div_table[] = {
 	{ 0x0, 2 },
 	{ 0x1, 2 },
@@ -486,6 +487,11 @@ static int aspeed_g6_clk_probe(struct platform_device *pdev)
 		return PTR_ERR(hw);
 	aspeed_g6_clk_data->hws[ASPEED_CLK_SDIO] = hw;
 
+	/* MAC1/2 RMII 50MHz RCLK */
+	hw = clk_hw_register_fixed_rate(dev, "mac12rclk", "hpll", 0, 50000000);
+	if (IS_ERR(hw))
+		return PTR_ERR(hw);
+
 	/* MAC1/2 AHB bus clock divider */
 	hw = clk_hw_register_divider_table(dev, "mac12", "hpll", 0,
 			scu_g6_base + ASPEED_G6_CLK_SELECTION1, 16, 3, 0,
@@ -495,6 +501,27 @@ static int aspeed_g6_clk_probe(struct platform_device *pdev)
 		return PTR_ERR(hw);
 	aspeed_g6_clk_data->hws[ASPEED_CLK_MAC12] = hw;
 
+	/* RMII1 50MHz (RCLK) output enable */
+	hw = clk_hw_register_gate(dev, "mac1rclk", "mac12rclk", 0,
+			scu_g6_base + ASPEED_MAC12_CLK_DLY, 29, 0,
+			&aspeed_g6_clk_lock);
+	if (IS_ERR(hw))
+		return PTR_ERR(hw);
+	aspeed_g6_clk_data->hws[ASPEED_CLK_MAC1RCLK] = hw;
+
+	/* RMII2 50MHz (RCLK) output enable */
+	hw = clk_hw_register_gate(dev, "mac2rclk", "mac12rclk", 0,
+			scu_g6_base + ASPEED_MAC12_CLK_DLY, 30, 0,
+			&aspeed_g6_clk_lock);
+	if (IS_ERR(hw))
+		return PTR_ERR(hw);
+	aspeed_g6_clk_data->hws[ASPEED_CLK_MAC2RCLK] = hw;
+
+	/* MAC1/2 RMII 50MHz RCLK */
+	hw = clk_hw_register_fixed_rate(dev, "mac34rclk", "hclk", 0, 50000000);
+	if (IS_ERR(hw))
+		return PTR_ERR(hw);
+
 	/* MAC3/4 AHB bus clock divider */
 	hw = clk_hw_register_divider_table(dev, "mac34", "hpll", 0,
 			scu_g6_base + 0x310, 24, 3, 0,
@@ -504,6 +531,22 @@ static int aspeed_g6_clk_probe(struct platform_device *pdev)
 		return PTR_ERR(hw);
 	aspeed_g6_clk_data->hws[ASPEED_CLK_MAC34] = hw;
 
+	/* RMII3 50MHz (RCLK) output enable */
+	hw = clk_hw_register_gate(dev, "mac3rclk", "mac34rclk", 0,
+			scu_g6_base + ASPEED_MAC34_CLK_DLY, 29, 0,
+			&aspeed_g6_clk_lock);
+	if (IS_ERR(hw))
+		return PTR_ERR(hw);
+	aspeed_g6_clk_data->hws[ASPEED_CLK_MAC3RCLK] = hw;
+
+	/* RMII4 50MHz (RCLK) output enable */
+	hw = clk_hw_register_gate(dev, "mac4rclk", "mac34rclk", 0,
+			scu_g6_base + ASPEED_MAC34_CLK_DLY, 30, 0,
+			&aspeed_g6_clk_lock);
+	if (IS_ERR(hw))
+		return PTR_ERR(hw);
+	aspeed_g6_clk_data->hws[ASPEED_CLK_MAC4RCLK] = hw;
+
 	/* LPC Host (LHCLK) clock divider */
 	hw = clk_hw_register_divider_table(dev, "lhclk", "hpll", 0,
 			scu_g6_base + ASPEED_G6_CLK_SELECTION1, 20, 3, 0,