diff options
| author |   Daniel Mack <daniel@zonque.org> | 2022-01-25 10:33:35 +0100 |
|---|---|---|
| committer |   Stephen Boyd <sboyd@kernel.org> | 2022-01-25 14:23:16 -0800 |
| commit | 2f3d32fe9df80a65485c548a145916145fc99d68 (patch) | |
| tree | 25f856c741e9c14948e374ddbde7df9874b5b3ed /drivers/clk/clk-cs2000-cp.c | |
| parent | clk: cs2000-cp: make clock skip setting configurable (diff) | |
| download | wireguard-linux-2f3d32fe9df80a65485c548a145916145fc99d68.tar.xz wireguard-linux-2f3d32fe9df80a65485c548a145916145fc99d68.zip | |
clk: cs2000-cp: freeze config during register fiddling
Make sure to freeze the configuration of the chip during the programming
of 32-bit registers. This avoids the processing of invalid intermediate
states.
Signed-off-by: Daniel Mack <daniel@zonque.org>
Link: https://lore.kernel.org/r/20220125093336.226787-9-daniel@zonque.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/clk-cs2000-cp.c')
| -rw-r--r-- | drivers/clk/clk-cs2000-cp.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/drivers/clk/clk-cs2000-cp.c b/drivers/clk/clk-cs2000-cp.c index 9f99e39b41f2..1baf0595ba59 100644 --- a/drivers/clk/clk-cs2000-cp.c +++ b/drivers/clk/clk-cs2000-cp.c @@ -52,6 +52,7 @@ #define FRACNSRC_DYNAMIC (1 << 0) /* GLOBAL_CFG */ +#define FREEZE (1 << 7) #define ENDEV2 (0x1) /* FUNC_CFG1 */ @@ -335,6 +336,10 @@ static int __cs2000_set_rate(struct cs2000_priv *priv, int ch, { int ret; + ret = cs2000_bset(priv, GLOBAL_CFG, FREEZE, FREEZE); + if (ret < 0) + return ret; + ret = cs2000_select_ratio_mode(priv, rate, parent_rate); if (ret < 0) return ret; @@ -347,6 +352,10 @@ static int __cs2000_set_rate(struct cs2000_priv *priv, int ch, if (ret < 0) return ret; + ret = cs2000_bset(priv, GLOBAL_CFG, FREEZE, 0); + if (ret < 0) + return ret; + priv->saved_rate = rate; priv->saved_parent_rate = parent_rate; |