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| author |   Anson Huang <anson.huang@nxp.com> | 2018-11-30 06:31:40 +0000 |
|---|---|---|
| committer |   Stephen Boyd <sboyd@kernel.org> | 2018-12-10 11:34:50 -0800 |
| commit | 929914946fa615889d176568b175984e5128e0a3 (patch) | |
| tree | 9625f891df449a70ff7cecfa785333234cb2f016 /drivers/clk/clk-fractional-divider.c | |
| parent | clk: imx6sl: ensure MMDC CH0 handshake is bypassed (diff) | |
| download | wireguard-linux-929914946fa615889d176568b175984e5128e0a3.tar.xz wireguard-linux-929914946fa615889d176568b175984e5128e0a3.zip | |
clk: imx6q: add DCICx clocks gate
On i.MX6QP/i.MX6Q/i.MX6DL, there are DCIC1/DCIC2 clocks
gate in CCM_CCGR0 register, add them into clock tree for
clock management.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/clk-fractional-divider.c')
0 files changed, 0 insertions, 0 deletions