diff options
| author |   A.s. Dong <aisheng.dong@nxp.com> | 2018-11-14 13:01:39 +0000 |
|---|---|---|
| committer |   Stephen Boyd <sboyd@kernel.org> | 2018-12-03 11:31:24 -0800 |
| commit | e983da27f70e8d29f4ae7262d52e4d07129498f3 (patch) | |
| tree | 595b5d52cc4c85ac86e31c70d47a4f64b51c5944 /drivers/clk/clk-fractional-divider.c | |
| parent | clk: imx: add gatable clock divider support (diff) | |
| download | wireguard-linux-e983da27f70e8d29f4ae7262d52e4d07129498f3.tar.xz wireguard-linux-e983da27f70e8d29f4ae7262d52e4d07129498f3.zip | |
clk: fractional-divider: add CLK_FRAC_DIVIDER_ZERO_BASED flag support
Adding CLK_FRAC_DIVIDER_ZERO_BASED flag to indicate the numerator and
denominator value in register are start from 0.
This can be used to support frac dividers like below:
Divider output clock = Divider input clock x [(frac +1) / (div +1)]
where frac/div in register is:
000b - Divide by 1.
001b - Divide by 2.
010b - Divide by 3.
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/clk-fractional-divider.c')
| -rw-r--r-- | drivers/clk/clk-fractional-divider.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/clk/clk-fractional-divider.c b/drivers/clk/clk-fractional-divider.c index fdf625fb10fa..7ccde6bd8dd5 100644 --- a/drivers/clk/clk-fractional-divider.c +++ b/drivers/clk/clk-fractional-divider.c @@ -40,6 +40,11 @@ static unsigned long clk_fd_recalc_rate(struct clk_hw *hw, m = (val & fd->mmask) >> fd->mshift; n = (val & fd->nmask) >> fd->nshift; + if (fd->flags & CLK_FRAC_DIVIDER_ZERO_BASED) { + m++; + n++; + } + if (!n || !m) return parent_rate; @@ -103,6 +108,11 @@ static int clk_fd_set_rate(struct clk_hw *hw, unsigned long rate, GENMASK(fd->mwidth - 1, 0), GENMASK(fd->nwidth - 1, 0), &m, &n); + if (fd->flags & CLK_FRAC_DIVIDER_ZERO_BASED) { + m--; + n--; + } + if (fd->lock) spin_lock_irqsave(fd->lock, flags); else |