diff options
| author |   Shawn Guo <shawn.guo@linaro.org> | 2018-01-24 19:48:26 +0800 |
|---|---|---|
| committer |   Shawn Guo <shawnguo@kernel.org> | 2018-02-27 09:19:12 +0800 |
| commit | a44d1f531a39da8cd6497372e713f5998b2d67af (patch) | |
| tree | f8dcec7acfd547c9cace2bbbc0351d16c3ae9b4d /drivers/clk/hisilicon/crg-hi3798cv200.c | |
| parent | clk: hi3798cv200: add support for HISTB_USB2_OTG_UTMI_CLK (diff) | |
| download | wireguard-linux-a44d1f531a39da8cd6497372e713f5998b2d67af.tar.xz wireguard-linux-a44d1f531a39da8cd6497372e713f5998b2d67af.zip | |
clk: hi3798cv200: fix define indentation
It's a coding-style fix, which corrects the indentation for all those
clock definitions, so that the code looks nicer and new definitions can
be added with a recommended indentation.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Diffstat (limited to 'drivers/clk/hisilicon/crg-hi3798cv200.c')
| -rw-r--r-- | drivers/clk/hisilicon/crg-hi3798cv200.c | 48 |
1 files changed, 24 insertions, 24 deletions
diff --git a/drivers/clk/hisilicon/crg-hi3798cv200.c b/drivers/clk/hisilicon/crg-hi3798cv200.c index 6017ade0cd92..451830e08375 100644 --- a/drivers/clk/hisilicon/crg-hi3798cv200.c +++ b/drivers/clk/hisilicon/crg-hi3798cv200.c @@ -27,30 +27,30 @@ #include "reset.h" /* hi3798CV200 core CRG */ -#define HI3798CV200_INNER_CLK_OFFSET 64 -#define HI3798CV200_FIXED_24M 65 -#define HI3798CV200_FIXED_25M 66 -#define HI3798CV200_FIXED_50M 67 -#define HI3798CV200_FIXED_75M 68 -#define HI3798CV200_FIXED_100M 69 -#define HI3798CV200_FIXED_150M 70 -#define HI3798CV200_FIXED_200M 71 -#define HI3798CV200_FIXED_250M 72 -#define HI3798CV200_FIXED_300M 73 -#define HI3798CV200_FIXED_400M 74 -#define HI3798CV200_MMC_MUX 75 -#define HI3798CV200_ETH_PUB_CLK 76 -#define HI3798CV200_ETH_BUS_CLK 77 -#define HI3798CV200_ETH_BUS0_CLK 78 -#define HI3798CV200_ETH_BUS1_CLK 79 -#define HI3798CV200_COMBPHY1_MUX 80 -#define HI3798CV200_FIXED_12M 81 -#define HI3798CV200_FIXED_48M 82 -#define HI3798CV200_FIXED_60M 83 -#define HI3798CV200_FIXED_166P5M 84 -#define HI3798CV200_SDIO0_MUX 85 - -#define HI3798CV200_CRG_NR_CLKS 128 +#define HI3798CV200_INNER_CLK_OFFSET 64 +#define HI3798CV200_FIXED_24M 65 +#define HI3798CV200_FIXED_25M 66 +#define HI3798CV200_FIXED_50M 67 +#define HI3798CV200_FIXED_75M 68 +#define HI3798CV200_FIXED_100M 69 +#define HI3798CV200_FIXED_150M 70 +#define HI3798CV200_FIXED_200M 71 +#define HI3798CV200_FIXED_250M 72 +#define HI3798CV200_FIXED_300M 73 +#define HI3798CV200_FIXED_400M 74 +#define HI3798CV200_MMC_MUX 75 +#define HI3798CV200_ETH_PUB_CLK 76 +#define HI3798CV200_ETH_BUS_CLK 77 +#define HI3798CV200_ETH_BUS0_CLK 78 +#define HI3798CV200_ETH_BUS1_CLK 79 +#define HI3798CV200_COMBPHY1_MUX 80 +#define HI3798CV200_FIXED_12M 81 +#define HI3798CV200_FIXED_48M 82 +#define HI3798CV200_FIXED_60M 83 +#define HI3798CV200_FIXED_166P5M 84 +#define HI3798CV200_SDIO0_MUX 85 + +#define HI3798CV200_CRG_NR_CLKS 128 static const struct hisi_fixed_rate_clock hi3798cv200_fixed_rate_clks[] = { { HISTB_OSC_CLK, "clk_osc", NULL, 0, 24000000, }, |