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| author |   Jonathan Neuschäfer <j.neuschaefer@gmx.net> | 2022-02-18 01:09:18 +0100 |
|---|---|---|
| committer |   Stephen Boyd <sboyd@kernel.org> | 2022-03-11 18:13:24 -0800 |
| commit | 3eb00f89162e80083dfcaa842468b510462cfeaa (patch) | |
| tree | b9839b21229f2ff773f330a2bb43471d65a33f24 /drivers/clk/hisilicon | |
| parent | clk: actions: Terminate clk_div_table with sentinel element (diff) | |
| download | wireguard-linux-3eb00f89162e80083dfcaa842468b510462cfeaa.tar.xz wireguard-linux-3eb00f89162e80083dfcaa842468b510462cfeaa.zip | |
clk: loongson1: Terminate clk_div_table with sentinel element
In order that the end of a clk_div_table can be detected, it must be
terminated with a sentinel element (.div = 0).
Fixes: b4626a7f4892 ("CLK: Add Loongson1C clock support")
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Link: https://lore.kernel.org/r/20220218000922.134857-3-j.neuschaefer@gmx.net
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/hisilicon')
0 files changed, 0 insertions, 0 deletions