diff options
| author |   Chen Jun <chenjun14@huawei.com> | 2017-05-26 15:38:19 +0800 |
|---|---|---|
| committer |   Stephen Boyd <sboyd@codeaurora.org> | 2017-06-19 18:00:20 -0700 |
| commit | 73908acb1e4afc7bc55354239597ac5e77098fb2 (patch) | |
| tree | e353e15b6c3f79a571c31430b07d7ba9d713f267 /drivers/clk/hisilicon | |
| parent | clk: gcc-msm8916: add support to 9.6MHz codec clk (diff) | |
| download | wireguard-linux-73908acb1e4afc7bc55354239597ac5e77098fb2.tar.xz wireguard-linux-73908acb1e4afc7bc55354239597ac5e77098fb2.zip | |
clk: hi3660: fix wrong parent name of clk_mux_sysbus
Parent name of clk_mux_sysbus is not correct. This patch fixes it.
Signed-off-by: Chen Jun <chenjun14@huawei.com>
Signed-off-by: John Stultz <john.stultz@linaro.org>
Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
Acked-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/hisilicon')
| -rw-r--r-- | drivers/clk/hisilicon/clk-hi3660.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/drivers/clk/hisilicon/clk-hi3660.c b/drivers/clk/hisilicon/clk-hi3660.c index 3bc5efba5fad..c5044e5e1fe6 100644 --- a/drivers/clk/hisilicon/clk-hi3660.c +++ b/drivers/clk/hisilicon/clk-hi3660.c @@ -206,6 +206,8 @@ static const struct hisi_gate_clock hi3660_crgctrl_gate_clks[] = { }; static const char *const +clk_mux_sysbus_p[] = {"clk_ppll1", "clk_ppll0"}; +static const char *const clk_mux_sdio_sys_p[] = {"clk_factor_mmc", "clk_div_sdio",}; static const char *const clk_mux_sd_sys_p[] = {"clk_factor_mmc", "clk_div_sd",}; @@ -239,8 +241,8 @@ static const char *const clk_mux_i2c_p[] = {"clkin_sys", "clk_div_i2c",}; static const struct hisi_mux_clock hi3660_crgctrl_mux_clks[] = { - { HI3660_CLK_MUX_SYSBUS, "clk_mux_sysbus", clk_mux_sdio_sys_p, - ARRAY_SIZE(clk_mux_sdio_sys_p), CLK_SET_RATE_PARENT, 0xac, 0, 1, + { HI3660_CLK_MUX_SYSBUS, "clk_mux_sysbus", clk_mux_sysbus_p, + ARRAY_SIZE(clk_mux_sysbus_p), CLK_SET_RATE_PARENT, 0xac, 0, 1, CLK_MUX_HIWORD_MASK, }, { HI3660_CLK_MUX_UART0, "clk_mux_uart0", clk_mux_uart0_p, ARRAY_SIZE(clk_mux_uart0_p), CLK_SET_RATE_PARENT, 0xac, 2, 1, |