diff options
| author |   Marek Vasut <marex@denx.de> | 2024-05-31 22:26:26 +0200 |
|---|---|---|
| committer |   Abel Vesa <abel.vesa@linaro.org> | 2024-06-21 09:35:30 +0300 |
| commit | ff06ea04e4cf3ba2f025024776e83bfbdfa05155 (patch) | |
| tree | 9617f48cdf5fa666fa3bee09d15a7e0211c2ed21 /drivers/clk/imx/clk.h | |
| parent | clk: imx: fracn-gppll: update rate table (diff) | |
| download | wireguard-linux-ff06ea04e4cf3ba2f025024776e83bfbdfa05155.tar.xz wireguard-linux-ff06ea04e4cf3ba2f025024776e83bfbdfa05155.zip | |
clk: imx: clk-imx8mp: Allow media_disp pixel clock reconfigure parent rate
The media_disp[12]_pix clock supply LCDIFv3 pixel clock output. These
clocks are usually the only downstream clock from Video PLL on i.MX8MP.
Allow these clocks to reconfigure the Video PLL, as that results in
accurate pixel clock. If the Video PLL is not reconfigured, the pixel
clock accuracy is low.
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20240531202648.277078-1-marex@denx.de
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Diffstat (limited to 'drivers/clk/imx/clk.h')
| -rw-r--r-- | drivers/clk/imx/clk.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index adb7ad649a0d..aa5202f284f3 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -442,6 +442,10 @@ struct clk_hw *__imx8m_clk_hw_composite(const char *name, _imx8m_clk_hw_composite(name, parent_names, reg, \ IMX_COMPOSITE_BUS, IMX_COMPOSITE_CLK_FLAGS_DEFAULT) +#define imx8m_clk_hw_composite_bus_flags(name, parent_names, reg, flags) \ + _imx8m_clk_hw_composite(name, parent_names, reg, \ + IMX_COMPOSITE_BUS, IMX_COMPOSITE_CLK_FLAGS_DEFAULT | flags) + #define imx8m_clk_hw_composite_bus_critical(name, parent_names, reg) \ _imx8m_clk_hw_composite(name, parent_names, reg, \ IMX_COMPOSITE_BUS, IMX_COMPOSITE_CLK_FLAGS_CRITICAL) |