diff options
| author |   Paul Cercueil <paul@crapouillou.net> | 2021-05-30 17:49:20 +0100 |
|---|---|---|
| committer |   Stephen Boyd <sboyd@kernel.org> | 2021-06-27 19:49:17 -0700 |
| commit | 315a8423b20362bb675c5263cb237ecb51d9589e (patch) | |
| tree | d825089180430a25bac03c53e7d4da22b566c7e9 /drivers/clk/ingenic | |
| parent | clk: Support bypassing dividers (diff) | |
| download | wireguard-linux-315a8423b20362bb675c5263cb237ecb51d9589e.tar.xz wireguard-linux-315a8423b20362bb675c5263cb237ecb51d9589e.zip | |
clk: ingenic: Read bypass register only when there is one
Rework the clock code so that the bypass register is only read when
there is actually a bypass functionality.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Link: https://lore.kernel.org/r/20210530164923.18134-4-paul@crapouillou.net
Tested-by: 周琰杰 (Zhou Yanjie)<zhouyanjie@wanyeetech.com> # on CU1830-neo/X1830
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/ingenic')
| -rw-r--r-- | drivers/clk/ingenic/cgu.c | 19 |
1 files changed, 11 insertions, 8 deletions
diff --git a/drivers/clk/ingenic/cgu.c b/drivers/clk/ingenic/cgu.c index 0619d45a950c..7686072aff8f 100644 --- a/drivers/clk/ingenic/cgu.c +++ b/drivers/clk/ingenic/cgu.c @@ -99,13 +99,14 @@ ingenic_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) od_enc = ctl >> pll_info->od_shift; od_enc &= GENMASK(pll_info->od_bits - 1, 0); - ctl = readl(cgu->base + pll_info->bypass_reg); + if (!pll_info->no_bypass_bit) { + ctl = readl(cgu->base + pll_info->bypass_reg); - bypass = !pll_info->no_bypass_bit && - !!(ctl & BIT(pll_info->bypass_bit)); + bypass = !!(ctl & BIT(pll_info->bypass_bit)); - if (bypass) - return parent_rate; + if (bypass) + return parent_rate; + } for (od = 0; od < pll_info->od_max; od++) { if (pll_info->od_encoding[od] == od_enc) @@ -225,11 +226,13 @@ static int ingenic_pll_enable(struct clk_hw *hw) u32 ctl; spin_lock_irqsave(&cgu->lock, flags); - ctl = readl(cgu->base + pll_info->bypass_reg); + if (!pll_info->no_bypass_bit) { + ctl = readl(cgu->base + pll_info->bypass_reg); - ctl &= ~BIT(pll_info->bypass_bit); + ctl &= ~BIT(pll_info->bypass_bit); - writel(ctl, cgu->base + pll_info->bypass_reg); + writel(ctl, cgu->base + pll_info->bypass_reg); + } ctl = readl(cgu->base + pll_info->reg); |