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| author |   Geliang Tang <geliangtang@163.com> | 2015-10-18 23:31:12 +0800 |
|---|---|---|
| committer |   Stephen Boyd <sboyd@codeaurora.org> | 2015-10-19 15:29:09 -0700 |
| commit | b30c64508b4131ceacc4b8fd9f01a78e1b1794bf (patch) | |
| tree | c58704feaef8fc149e92d97a7656c0fd4ff230d9 /drivers/clk/keystone | |
| parent | clk: mvebu: Use of_clk_get_parent_name() (diff) | |
| download | wireguard-linux-b30c64508b4131ceacc4b8fd9f01a78e1b1794bf.tar.xz wireguard-linux-b30c64508b4131ceacc4b8fd9f01a78e1b1794bf.zip | |
clk: keystone: fix a trivial typo
s/regsiter/register/
Signed-off-by: Geliang Tang <geliangtang@163.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/keystone')
| -rw-r--r-- | drivers/clk/keystone/pll.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/keystone/pll.c b/drivers/clk/keystone/pll.c index 3f553d0ae0b5..a26ba2184454 100644 --- a/drivers/clk/keystone/pll.c +++ b/drivers/clk/keystone/pll.c @@ -157,7 +157,7 @@ out: * _of_clk_init - PLL initialisation via DT * @node: device tree node for this clock * @pllctrl: If true, lower 6 bits of multiplier is in pllm register of - * pll controller, else it is in the control regsiter0(bit 11-6) + * pll controller, else it is in the control register0(bit 11-6) */ static void __init _of_pll_clk_init(struct device_node *node, bool pllctrl) { |