diff options
| author |   Alexandre Mergnat <amergnat@baylibre.com> | 2019-07-25 18:42:36 +0200 |
|---|---|---|
| committer |   Jerome Brunet <jbrunet@baylibre.com> | 2019-07-29 12:42:49 +0200 |
| commit | 3a36044e7f3909c7ddb7ddfc727ab8104a563439 (patch) | |
| tree | d2d271b937b6c05150b5d20d480d4dd356ba6f07 /drivers/clk/meson/axg.c | |
| parent | clk: meson: meson8b: migrate to the new parent description method (diff) | |
| download | wireguard-linux-3a36044e7f3909c7ddb7ddfc727ab8104a563439.tar.xz wireguard-linux-3a36044e7f3909c7ddb7ddfc727ab8104a563439.zip | |
clk: meson: clk-regmap: migrate to new parent description method
This clock controller use the string comparison method to describe parent
relation between the clocks, which is not optimized.
Migrate to the new way by using .parent_hws where possible (ie. when
all clocks are local to the controller) and use .parent_data otherwise.
Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Diffstat (limited to 'drivers/clk/meson/axg.c')
| -rw-r--r-- | drivers/clk/meson/axg.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c index 7a3d795cc614..13fc0006f63d 100644 --- a/drivers/clk/meson/axg.c +++ b/drivers/clk/meson/axg.c @@ -1096,6 +1096,9 @@ static struct clk_regmap axg_gen_clk = { }, }; +#define MESON_GATE(_name, _reg, _bit) \ + MESON_PCLK(_name, _reg, _bit, &axg_clk81.hw) + /* Everything Else (EE) domain gates */ static MESON_GATE(axg_ddr, HHI_GCLK_MPEG0, 0); static MESON_GATE(axg_audio_locker, HHI_GCLK_MPEG0, 2); |