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| author |   Kevin Hilman <khilman@baylibre.com> | 2017-04-04 15:58:11 -0700 |
|---|---|---|
| committer | Kevin Hilman <khilman@baylibre.com> | 2017-04-04 15:58:11 -0700 |
| commit | 3a429818a2e48928ae0114df5fb3b0612dd57001 (patch) | |
| tree | 7f0f6b1eb5aa70b6b7f0acfa1991cedd1d8badf8 /drivers/clk/meson/gxbb.h | |
| parent | dt-bindings: clock: gxbb-clkc: Add GXL compatible variant (diff) | |
| parent | clk: meson-gxbb: Add GXL/GXM GP0 Variant (diff) | |
| download | wireguard-linux-3a429818a2e48928ae0114df5fb3b0612dd57001.tar.xz wireguard-linux-3a429818a2e48928ae0114df5fb3b0612dd57001.zip | |
Merge branch 'v4.12/clk-drivers' into v4.12/clk
* v4.12/clk-drivers:
clk: meson-gxbb: Add GXL/GXM GP0 Variant
clk: meson-gxbb: Add GP0 PLL init parameters
clk: meson: Add support for parameters for specific PLLs
clk: meson-gxbb: Add MALI clocks
clk: meson: mpll: correct N2 maximum value
clk: meson8b: add the mplls clocks 0, 1 and 2
clk: meson: gxbb: mpll: use rw operation
clk: meson: mpll: add rw operation
clk: gxbb: put dividers and muxes in tables
clk: meson8b: put dividers and muxes in tables
clk: meson: add missing const qualifiers on gate arrays
clk: meson: fix SET_PARM macro
Diffstat (limited to 'drivers/clk/meson/gxbb.h')
| -rw-r--r-- | drivers/clk/meson/gxbb.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h index e5c49923a24b..9d949244b104 100644 --- a/drivers/clk/meson/gxbb.h +++ b/drivers/clk/meson/gxbb.h @@ -71,6 +71,8 @@ #define HHI_GP0_PLL_CNTL2 0x44 /* 0x11 offset in data sheet */ #define HHI_GP0_PLL_CNTL3 0x48 /* 0x12 offset in data sheet */ #define HHI_GP0_PLL_CNTL4 0x4c /* 0x13 offset in data sheet */ +#define HHI_GP0_PLL_CNTL5 0x50 /* 0x14 offset in data sheet */ +#define HHI_GP0_PLL_CNTL1 0x58 /* 0x16 offset in data sheet */ #define HHI_XTAL_DIVN_CNTL 0xbc /* 0x2f offset in data sheet */ #define HHI_TIMER90K 0xec /* 0x3b offset in data sheet */ |