diff options
| author |   Jerome Brunet <jbrunet@baylibre.com> | 2018-01-19 16:55:27 +0100 |
|---|---|---|
| committer | Jerome Brunet <jbrunet@baylibre.com> | 2018-02-12 09:49:23 +0100 |
| commit | 3c4fe763d64db93c0c8ec359cf394cfc491f91f3 (patch) | |
| tree | c9b149483bb2edd7f6b79e595365ed470ef5a54a /drivers/clk/meson/gxbb.h | |
| parent | clk: meson: add the gxl hdmi pll (diff) | |
| download | wireguard-linux-3c4fe763d64db93c0c8ec359cf394cfc491f91f3.tar.xz wireguard-linux-3c4fe763d64db93c0c8ec359cf394cfc491f91f3.zip | |
clk: meson: fix rate calculation of plls with a fractional part
The rate of the parent should not be multiplied by 2 when the pll has a
fractional part. This is making the rate calculation of the gxl_hdmi_pll
wrong (and others as well). This multiplication is specific
to the hdmi_pll of gxbb and is most likely due to a multiplier sitting
in front of this particular pll.
Add a fixed factor clock in front on the gxbb pll and remove this constant
from the calculation to fix the problem
Fixes: 4a47295144dd ("clk: meson: fractional pll support")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Diffstat (limited to 'drivers/clk/meson/gxbb.h')
| -rw-r--r-- | drivers/clk/meson/gxbb.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h index aee6fbba2004..42573b28a137 100644 --- a/drivers/clk/meson/gxbb.h +++ b/drivers/clk/meson/gxbb.h @@ -194,8 +194,9 @@ #define CLKID_VPU_1_DIV 130 #define CLKID_VAPB_0_DIV 134 #define CLKID_VAPB_1_DIV 137 +#define CLKID_HDMI_PLL_PRE_MULT 141 -#define NR_CLKS 141 +#define NR_CLKS 142 /* include the CLKIDs that have been made part of the DT binding */ #include <dt-bindings/clock/gxbb-clkc.h> |