diff options
| author |   Andrew Bresticker <abrestic@chromium.org> | 2015-02-24 19:56:03 -0800 |
|---|---|---|
| committer |   Ralf Baechle <ralf@linux-mips.org> | 2015-03-31 11:59:04 +0200 |
| commit | 43049b0c83f177083a56d69e64e47c82bcc04185 (patch) | |
| tree | b5a77282449ac612c44b42aea1fbdb76ad1c31e8 /drivers/clk/pistachio/clk.h | |
| parent | CLK: Add basic infrastructure for Pistachio clocks (diff) | |
| download | wireguard-linux-43049b0c83f177083a56d69e64e47c82bcc04185.tar.xz wireguard-linux-43049b0c83f177083a56d69e64e47c82bcc04185.zip | |
CLK: Pistachio: Add PLL driver
Add a driver for the integer (GF40LP_LAINT) and fractional (GF40LP_FRAC)
PLLs present on Pistachio.
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: devicetree@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: Ezequiel Garcia <ezequiel.garcia@imgtec.com>
Cc: James Hartley <james.hartley@imgtec.com>
Cc: James Hogan <james.hogan@imgtec.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Patchwork: https://patchwork.linux-mips.org/patch/9316/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'drivers/clk/pistachio/clk.h')
| -rw-r--r-- | drivers/clk/pistachio/clk.h | 50 |
1 files changed, 50 insertions, 0 deletions
diff --git a/drivers/clk/pistachio/clk.h b/drivers/clk/pistachio/clk.h index e735107ddab0..52fabbc24624 100644 --- a/drivers/clk/pistachio/clk.h +++ b/drivers/clk/pistachio/clk.h @@ -94,6 +94,53 @@ struct pistachio_fixed_factor { .parent = _pname, \ } +struct pistachio_pll_rate_table { + unsigned long fref; + unsigned long fout; + unsigned int refdiv; + unsigned int fbdiv; + unsigned int postdiv1; + unsigned int postdiv2; + unsigned int frac; +}; + +enum pistachio_pll_type { + PLL_GF40LP_LAINT, + PLL_GF40LP_FRAC, +}; + +struct pistachio_pll { + unsigned int id; + unsigned long reg_base; + enum pistachio_pll_type type; + struct pistachio_pll_rate_table *rates; + unsigned int nr_rates; + const char *name; + const char *parent; +}; + +#define PLL(_id, _name, _pname, _type, _reg, _rates) \ + { \ + .id = _id, \ + .reg_base = _reg, \ + .type = _type, \ + .rates = _rates, \ + .nr_rates = ARRAY_SIZE(_rates), \ + .name = _name, \ + .parent = _pname, \ + } + +#define PLL_FIXED(_id, _name, _pname, _type, _reg) \ + { \ + .id = _id, \ + .reg_base = _reg, \ + .type = _type, \ + .rates = NULL, \ + .nr_rates = 0, \ + .name = _name, \ + .parent = _pname, \ + } + struct pistachio_clk_provider { struct device_node *node; void __iomem *base; @@ -117,6 +164,9 @@ extern void pistachio_clk_register_fixed_factor(struct pistachio_clk_provider *p, struct pistachio_fixed_factor *ff, unsigned int num); +extern void pistachio_clk_register_pll(struct pistachio_clk_provider *p, + struct pistachio_pll *pll, + unsigned int num); extern void pistachio_clk_force_enable(struct pistachio_clk_provider *p, unsigned int *clk_ids, unsigned int num); |