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| author |   Elaine Zhang <zhangqing@rock-chips.com> | 2022-10-18 17:14:07 +0200 |
|---|---|---|
| committer |   Heiko Stuebner <heiko@sntech.de> | 2022-11-15 11:37:41 +0100 |
| commit | f1c506d152ff235ad621d3c25d061cb16da67214 (patch) | |
| tree | 62f295cf3fcb13706e78dbcf0a6295893b03a649 /drivers/clk/rockchip/Kconfig | |
| parent | clk: rockchip: add lookup table support (diff) | |
| download | wireguard-linux-f1c506d152ff235ad621d3c25d061cb16da67214.tar.xz wireguard-linux-f1c506d152ff235ad621d3c25d061cb16da67214.zip | |
clk: rockchip: add clock controller for the RK3588
Add full clock controller support RK3588.
[rebase, integrate fixes from Wyon and Finley, add missing frequencies
to PLL lookup table, update commit message, add GATE_LINK clocks which
downstream handles in its own driver with one DT node per clock]
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Link: https://lore.kernel.org/r/20221018151407.63395-10-sebastian.reichel@collabora.com
[dropped module stuff after talking to Sebastian]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'drivers/clk/rockchip/Kconfig')
| -rw-r--r-- | drivers/clk/rockchip/Kconfig | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/clk/rockchip/Kconfig b/drivers/clk/rockchip/Kconfig index 345a5d2a457c..9aad86925cd2 100644 --- a/drivers/clk/rockchip/Kconfig +++ b/drivers/clk/rockchip/Kconfig @@ -99,4 +99,12 @@ config CLK_RK3568 default y help Build the driver for RK3568 Clock Driver. + +config CLK_RK3588 + bool "Rockchip RK3588 clock controller support" + depends on ARM64 || COMPILE_TEST + default y + help + Build the driver for RK3588 Clock Driver. + endif |