diff options
| author |   Chris Morgan <macromorgan@hotmail.com> | 2023-12-04 12:57:17 -0600 |
|---|---|---|
| committer |   Heiko Stuebner <heiko@sntech.de> | 2023-12-05 10:43:42 +0100 |
| commit | 685da6972647b486980c0cc8fd6bb5d3863fd6b7 (patch) | |
| tree | e99753bff348eb1fb1c969c5ecbf47ffe9eb933f /drivers/clk/rockchip | |
| parent | clk: rockchip: rk3568: Add PLL rate for 115.2MHz (diff) | |
| download | wireguard-linux-685da6972647b486980c0cc8fd6bb5d3863fd6b7.tar.xz wireguard-linux-685da6972647b486980c0cc8fd6bb5d3863fd6b7.zip | |
clk: rockchip: rk3568: Add PLL rate for 126.4MHz
Add support for a PLL rate of 126.4MHz so that the Powkiddy X55 panel
can run at a requested 60hz.
I have confirmed this rate fits with all the constraints
listed in the TRM for the VPLL (as an integer PLL) in Part 1 "Chapter
2 Clock & Reset Unit (CRU)."
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Link: https://lore.kernel.org/r/20231204185719.569021-9-macroalpha82@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'drivers/clk/rockchip')
| -rw-r--r-- | drivers/clk/rockchip/clk-rk3568.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c index 43185668daf6..497a7e51ffda 100644 --- a/drivers/clk/rockchip/clk-rk3568.c +++ b/drivers/clk/rockchip/clk-rk3568.c @@ -77,6 +77,7 @@ static struct rockchip_pll_rate_table rk3568_pll_rates[] = { RK3036_PLL_RATE(200000000, 1, 100, 3, 4, 1, 0), RK3036_PLL_RATE(148500000, 1, 99, 4, 4, 1, 0), RK3036_PLL_RATE(135000000, 2, 45, 4, 1, 1, 0), + RK3036_PLL_RATE(126400000, 1, 79, 5, 3, 1, 0), RK3036_PLL_RATE(119000000, 3, 119, 4, 2, 1, 0), RK3036_PLL_RATE(115200000, 1, 24, 5, 1, 1, 0), RK3036_PLL_RATE(108000000, 2, 45, 5, 1, 1, 0), |