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| author |   Alibek Omarov <a1ba.omarov@gmail.com> | 2023-06-14 16:47:16 +0300 |
|---|---|---|
| committer |   Heiko Stuebner <heiko@sntech.de> | 2023-07-10 12:11:26 +0200 |
| commit | 7f890a885f9a226ae1309b967d4e6fac933610db (patch) | |
| tree | 4846acfe4a11a59e985ad157e6d38324027d76ce /drivers/clk/rockchip | |
| parent | Linux 6.5-rc1 (diff) | |
| download | wireguard-linux-7f890a885f9a226ae1309b967d4e6fac933610db.tar.xz wireguard-linux-7f890a885f9a226ae1309b967d4e6fac933610db.zip | |
clk: rockchip: rk3568: Add PLL rate for 101MHz
This patch adds PLL setting for not so common resolution as 1920x720-50.00,
which can be set using 2500 horizontal signals and 808 vertical.
Signed-off-by: Alibek Omarov <a1ba.omarov@gmail.com>
Reviewed-by: Sascha Hauer <s.hauer@pengutronix.de>
Link: https://lore.kernel.org/r/20230614134716.1055862-1-a1ba.omarov@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'drivers/clk/rockchip')
| -rw-r--r-- | drivers/clk/rockchip/clk-rk3568.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c index f85902e2590c..5dae960af4ce 100644 --- a/drivers/clk/rockchip/clk-rk3568.c +++ b/drivers/clk/rockchip/clk-rk3568.c @@ -79,6 +79,7 @@ static struct rockchip_pll_rate_table rk3568_pll_rates[] = { RK3036_PLL_RATE(135000000, 2, 45, 4, 1, 1, 0), RK3036_PLL_RATE(119000000, 3, 119, 4, 2, 1, 0), RK3036_PLL_RATE(108000000, 2, 45, 5, 1, 1, 0), + RK3036_PLL_RATE(101000000, 1, 101, 6, 4, 1, 0), RK3036_PLL_RATE(100000000, 1, 150, 6, 6, 1, 0), RK3036_PLL_RATE(96000000, 1, 96, 6, 4, 1, 0), RK3036_PLL_RATE(78750000, 1, 96, 6, 4, 1, 0), |