diff options
| author |   Zong Li <zong.li@sifive.com> | 2022-03-04 18:03:17 +0800 |
|---|---|---|
| committer |   Stephen Boyd <sboyd@kernel.org> | 2022-03-15 15:56:28 -0700 |
| commit | e83da8e2a1c323021ecb57f9a738f08fdd7879f1 (patch) | |
| tree | 9c7f20f5b4c3355e8b05584aed47023dbe3014fe /drivers/clk/sifive | |
| parent | Linux 5.17-rc1 (diff) | |
| download | wireguard-linux-e83da8e2a1c323021ecb57f9a738f08fdd7879f1.tar.xz wireguard-linux-e83da8e2a1c323021ecb57f9a738f08fdd7879f1.zip | |
clk: sifive: duplicate the macro definitions for the time being
This is a temporary patch in whole patch set. We are going to change the
macro name in dt-binding, in order to avoid breaking the driver build
and git bisect, add these macro definitions for the time being, and we
will remove them later.
Signed-off-by: Zong Li <zong.li@sifive.com>
Link: https://lore.kernel.org/r/8cfd57f01cfb59adb716eb13ca0c8250c246dcb2.1646388139.git.zong.li@sifive.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/sifive')
| -rw-r--r-- | drivers/clk/sifive/fu540-prci.c | 6 | ||||
| -rw-r--r-- | drivers/clk/sifive/fu740-prci.c | 11 |
2 files changed, 15 insertions, 2 deletions
diff --git a/drivers/clk/sifive/fu540-prci.c b/drivers/clk/sifive/fu540-prci.c index 29bab915003c..9e13119066eb 100644 --- a/drivers/clk/sifive/fu540-prci.c +++ b/drivers/clk/sifive/fu540-prci.c @@ -20,9 +20,13 @@ #include <dt-bindings/clock/sifive-fu540-prci.h> -#include "fu540-prci.h" #include "sifive-prci.h" +#define PRCI_CLK_COREPLL 0 +#define PRCI_CLK_DDRPLL 1 +#define PRCI_CLK_GEMGXLPLL 2 +#define PRCI_CLK_TLCLK 3 + /* PRCI integration data for each WRPLL instance */ static struct __prci_wrpll_data __prci_corepll_data = { diff --git a/drivers/clk/sifive/fu740-prci.c b/drivers/clk/sifive/fu740-prci.c index 53f6e00a03b9..7141a22d90e3 100644 --- a/drivers/clk/sifive/fu740-prci.c +++ b/drivers/clk/sifive/fu740-prci.c @@ -8,9 +8,18 @@ #include <dt-bindings/clock/sifive-fu740-prci.h> -#include "fu540-prci.h" #include "sifive-prci.h" +#define PRCI_CLK_COREPLL 0 +#define PRCI_CLK_DDRPLL 1 +#define PRCI_CLK_GEMGXLPLL 2 +#define PRCI_CLK_DVFSCOREPLL 3 +#define PRCI_CLK_HFPCLKPLL 4 +#define PRCI_CLK_CLTXPLL 5 +#define PRCI_CLK_TLCLK 6 +#define PRCI_CLK_PCLK 7 +#define PRCI_CLK_PCIE_AUX 8 + /* PRCI integration data for each WRPLL instance */ static struct __prci_wrpll_data __prci_corepll_data = { |