diff options
author | Xingyu Wu <xingyu.wu@starfivetech.com> | 2023-07-13 19:38:57 +0800 |
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committer | Conor Dooley <conor.dooley@microchip.com> | 2023-07-19 18:08:05 +0100 |
commit | 81279f5d0812e154239789e6f0295ea3b25c0d46 (patch) | |
tree | 2857103cf647fcc42c1ff8b2e6bed549f0dd643b /drivers/clk/starfive/clk-starfive-jh7110.h | |
parent | clk: starfive: Add StarFive JH7110 System-Top-Group clock driver (diff) | |
download | wireguard-linux-81279f5d0812e154239789e6f0295ea3b25c0d46.tar.xz wireguard-linux-81279f5d0812e154239789e6f0295ea3b25c0d46.zip |
clk: starfive: Add StarFive JH7110 Image-Signal-Process clock driver
Add driver for the StarFive JH7110 Image-Signal-Process clock controller.
And these clock controllers should power on and enable the clocks from
SYSCRG before registering.
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Diffstat (limited to 'drivers/clk/starfive/clk-starfive-jh7110.h')
-rw-r--r-- | drivers/clk/starfive/clk-starfive-jh7110.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/clk/starfive/clk-starfive-jh7110.h b/drivers/clk/starfive/clk-starfive-jh7110.h index f29682b8d400..0659adae4d76 100644 --- a/drivers/clk/starfive/clk-starfive-jh7110.h +++ b/drivers/clk/starfive/clk-starfive-jh7110.h @@ -4,6 +4,12 @@ #include "clk-starfive-jh71x0.h" +/* top clocks of ISP/VOUT domain from JH7110 SYSCRG */ +struct jh7110_top_sysclk { + struct clk_bulk_data *top_clks; + int top_clks_num; +}; + int jh7110_reset_controller_register(struct jh71x0_clk_priv *priv, const char *adev_name, u32 adev_id); |