diff options
| author |   Icenowy Zheng <icenowy@aosc.xyz> | 2016-12-13 23:22:48 +0800 |
|---|---|---|
| committer |   Maxime Ripard <maxime.ripard@free-electrons.com> | 2017-01-02 22:24:55 +0100 |
| commit | bb021cda2ccf45ee9470bf0f8c55323ad1c761ae (patch) | |
| tree | 215b4d74e53bebc292329acb7046ac9e32a9e686 /drivers/clk/sunxi-ng/ccu-sun8i-a33.c | |
| parent | clk: sunxi-ng: fix PLL_CPUX adjusting on A33 (diff) | |
| download | wireguard-linux-bb021cda2ccf45ee9470bf0f8c55323ad1c761ae.tar.xz wireguard-linux-bb021cda2ccf45ee9470bf0f8c55323ad1c761ae.zip | |
clk: sunxi-ng: set the parent rate when adjustin CPUX clock on A33
The CPUX clock on A33, which is for the Cortex-A7 cores, is designed to
be changeable by changing the rate of PLL_CPUX.
Add CLK_SET_RATE_PARENT flag to this clock.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'drivers/clk/sunxi-ng/ccu-sun8i-a33.c')
| -rw-r--r-- | drivers/clk/sunxi-ng/ccu-sun8i-a33.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-a33.c b/drivers/clk/sunxi-ng/ccu-sun8i-a33.c index e1dc4e5b34e1..94f1c8beda8d 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-a33.c +++ b/drivers/clk/sunxi-ng/ccu-sun8i-a33.c @@ -170,7 +170,7 @@ static SUNXI_CCU_N_WITH_GATE_LOCK(pll_ddr1_clk, "pll-ddr1", static const char * const cpux_parents[] = { "osc32k", "osc24M", "pll-cpux" , "pll-cpux" }; static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents, - 0x050, 16, 2, CLK_IS_CRITICAL); + 0x050, 16, 2, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT); static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x050, 0, 2, 0); |