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authorMaxime Ripard <maxime.ripard@free-electrons.com>2016-06-29 21:05:23 +0200
committerMichael Turquette <mturquette@baylibre.com>2016-07-08 18:04:32 -0700
commit1d80c14248d6082c91a8a9e3d70cc94c3cc18ecb (patch)
tree9611710254ac9ce4cef789aed94c699497b7fb30 /drivers/clk/sunxi-ng/ccu_common.h
parentdt-bindings: sunxi: Add CCU binding documentation (diff)
downloadwireguard-linux-1d80c14248d6082c91a8a9e3d70cc94c3cc18ecb.tar.xz
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clk: sunxi-ng: Add common infrastructure
Start our new clock infrastructure by adding the registration code, common structure and common code. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20160629190535.11855-3-maxime.ripard@free-electrons.com
Diffstat (limited to 'drivers/clk/sunxi-ng/ccu_common.h')
-rw-r--r--drivers/clk/sunxi-ng/ccu_common.h85
1 files changed, 85 insertions, 0 deletions
diff --git a/drivers/clk/sunxi-ng/ccu_common.h b/drivers/clk/sunxi-ng/ccu_common.h
new file mode 100644
index 000000000000..b3d9abfbd721
--- /dev/null
+++ b/drivers/clk/sunxi-ng/ccu_common.h
@@ -0,0 +1,85 @@
+/*
+ * Copyright (c) 2016 Maxime Ripard. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _COMMON_H_
+#define _COMMON_H_
+
+#include <linux/compiler.h>
+#include <linux/clk-provider.h>
+
+#define CCU_FEATURE_FRACTIONAL BIT(0)
+#define CCU_FEATURE_VARIABLE_PREDIV BIT(1)
+#define CCU_FEATURE_FIXED_PREDIV BIT(2)
+#define CCU_FEATURE_FIXED_POSTDIV BIT(3)
+
+struct device_node;
+
+#define CLK_HW_INIT(_name, _parent, _ops, _flags) \
+ &(struct clk_init_data) { \
+ .flags = _flags, \
+ .name = _name, \
+ .parent_names = (const char *[]) { _parent }, \
+ .num_parents = 1, \
+ .ops = _ops, \
+ }
+
+#define CLK_HW_INIT_PARENTS(_name, _parents, _ops, _flags) \
+ &(struct clk_init_data) { \
+ .flags = _flags, \
+ .name = _name, \
+ .parent_names = _parents, \
+ .num_parents = ARRAY_SIZE(_parents), \
+ .ops = _ops, \
+ }
+
+#define CLK_FIXED_FACTOR(_struct, _name, _parent, \
+ _div, _mult, _flags) \
+ struct clk_fixed_factor _struct = { \
+ .div = _div, \
+ .mult = _mult, \
+ .hw.init = CLK_HW_INIT(_name, \
+ _parent, \
+ &clk_fixed_factor_ops, \
+ _flags), \
+ }
+
+struct ccu_common {
+ void __iomem *base;
+ u16 reg;
+
+ unsigned long features;
+ spinlock_t *lock;
+ struct clk_hw hw;
+};
+
+static inline struct ccu_common *hw_to_ccu_common(struct clk_hw *hw)
+{
+ return container_of(hw, struct ccu_common, hw);
+}
+
+struct sunxi_ccu_desc {
+ struct ccu_common **ccu_clks;
+ unsigned long num_ccu_clks;
+
+ struct clk_hw_onecell_data *hw_clks;
+
+ struct ccu_reset_map *resets;
+ unsigned long num_resets;
+};
+
+void ccu_helper_wait_for_lock(struct ccu_common *common, u32 lock);
+
+int sunxi_ccu_probe(struct device_node *node, void __iomem *reg,
+ const struct sunxi_ccu_desc *desc);
+
+#endif /* _COMMON_H_ */