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authorChen-Yu Tsai <wens@csie.org>2016-08-25 14:21:58 +0800
committerMaxime Ripard <maxime.ripard@free-electrons.com>2016-08-25 22:30:36 +0200
commit8adfb08605a99d742853ff8cf4da5bc68db2028a (patch)
tree48cf32d443456015e70f70d550380fffc265a708 /drivers/clk/sunxi-ng/ccu_mux.c
parentclk: sunxi-ng: mux: support fixed pre-dividers on multiple parents (diff)
downloadwireguard-linux-8adfb08605a99d742853ff8cf4da5bc68db2028a.tar.xz
wireguard-linux-8adfb08605a99d742853ff8cf4da5bc68db2028a.zip
clk: sunxi-ng: mux: Add clk notifier functions
On sunxi we support cpufreq by changing the clock rate of PLL-CPU. It's possible the clock output of the PLL goes out of the CPU's operational limits when the PLL's multipliers / dividers are changed and it hasn't stabilized yet. This would result in the CPU hanging. To circumvent this, we temporarily switch the CPU mux clock to another stable clock before the rate change, and switch it back after the PLL stabilizes. This is done with clk notifiers registered on the PLL. This patch adds common functions for notifiers to reparent mux clocks. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'drivers/clk/sunxi-ng/ccu_mux.c')
-rw-r--r--drivers/clk/sunxi-ng/ccu_mux.c36
1 files changed, 36 insertions, 0 deletions
diff --git a/drivers/clk/sunxi-ng/ccu_mux.c b/drivers/clk/sunxi-ng/ccu_mux.c
index 7b17e0c26b01..a43ad52a957d 100644
--- a/drivers/clk/sunxi-ng/ccu_mux.c
+++ b/drivers/clk/sunxi-ng/ccu_mux.c
@@ -8,7 +8,9 @@
* the License, or (at your option) any later version.
*/
+#include <linux/clk.h>
#include <linux/clk-provider.h>
+#include <linux/delay.h>
#include "ccu_gate.h"
#include "ccu_mux.h"
@@ -199,3 +201,37 @@ const struct clk_ops ccu_mux_ops = {
.determine_rate = __clk_mux_determine_rate,
.recalc_rate = ccu_mux_recalc_rate,
};
+
+/*
+ * This clock notifier is called when the frequency of the of the parent
+ * PLL clock is to be changed. The idea is to switch the parent to a
+ * stable clock, such as the main oscillator, while the PLL frequency
+ * stabilizes.
+ */
+static int ccu_mux_notifier_cb(struct notifier_block *nb,
+ unsigned long event, void *data)
+{
+ struct ccu_mux_nb *mux = to_ccu_mux_nb(nb);
+ int ret = 0;
+
+ if (event == PRE_RATE_CHANGE) {
+ mux->original_index = ccu_mux_helper_get_parent(mux->common,
+ mux->cm);
+ ret = ccu_mux_helper_set_parent(mux->common, mux->cm,
+ mux->bypass_index);
+ } else if (event == POST_RATE_CHANGE) {
+ ret = ccu_mux_helper_set_parent(mux->common, mux->cm,
+ mux->original_index);
+ }
+
+ udelay(mux->delay_us);
+
+ return notifier_from_errno(ret);
+}
+
+int ccu_mux_notifier_register(struct clk *clk, struct ccu_mux_nb *mux_nb)
+{
+ mux_nb->clk_nb.notifier_call = ccu_mux_notifier_cb;
+
+ return clk_notifier_register(clk, &mux_nb->clk_nb);
+}