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| author |   Thierry Reding <treding@nvidia.com> | 2015-04-20 15:13:36 +0200 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2016-04-28 12:41:50 +0200 |
| commit | a91bb605ec5f93676e503267c89469d02c5b4cbc (patch) | |
| tree | 1f692e3aa61cd951112d17416c3a86570ddbbac0 /drivers/clk/tegra/clk-id.h | |
| parent | clk: tegra: dpaux and dpaux1 are fixed factor clocks (diff) | |
| download | wireguard-linux-a91bb605ec5f93676e503267c89469d02c5b4cbc.tar.xz wireguard-linux-a91bb605ec5f93676e503267c89469d02c5b4cbc.zip | |
clk: tegra: Add sor_safe clock
The sor_safe clock is a fixed factor (1:17) clock derived from pll_p. It
has a gate bit in the peripheral clock registers. While the SOR is being
powered up, sor_safe can be used as the source until the SOR brick can
generate its own clock.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/clk/tegra/clk-id.h')
| -rw-r--r-- | drivers/clk/tegra/clk-id.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/tegra/clk-id.h b/drivers/clk/tegra/clk-id.h index fe6c6afcfa60..36c974916d4f 100644 --- a/drivers/clk/tegra/clk-id.h +++ b/drivers/clk/tegra/clk-id.h @@ -307,6 +307,7 @@ enum clk_id { tegra_clk_xusb_ss_div2, tegra_clk_xusb_ssp_src, tegra_clk_sclk_mux, + tegra_clk_sor_safe, tegra_clk_max, }; |