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| author |   Thierry Reding <treding@nvidia.com> | 2019-11-11 14:09:15 +0100 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2019-11-11 14:09:15 +0100 |
| commit | d1ee3173a139ed2eb8d87e06216f0426b16084d8 (patch) | |
| tree | a80f5b3cb7566450708d4aa5e25a14b5c4415c9a /drivers/clk/tegra/clk-id.h | |
| parent | Merge branch 'for-5.5/clk-core' into for-5.5/clk (diff) | |
| parent | dt-bindings: clock: tegra: Rename SOR0_LVDS to SOR0_OUT (diff) | |
| download | wireguard-linux-d1ee3173a139ed2eb8d87e06216f0426b16084d8.tar.xz wireguard-linux-d1ee3173a139ed2eb8d87e06216f0426b16084d8.zip | |
Merge branch 'for-5.5/dt-bindings' into for-5.5/clk
Diffstat (limited to 'drivers/clk/tegra/clk-id.h')
0 files changed, 0 insertions, 0 deletions